ModelSim SE User's Manual - Electrical and Computer Engineering

UM-366 14 - PSL Assertions
Writing assertions in an external file
Syntax
Restrictions
Example
ModelSim SE User’s Manual
Assertions in an external file are grouped in vunits and bound to a module or
entity/architecture.
vunit name ([])
{
default clock = ;
;
...
}
name – The name of the vunit.
– The hierarchical name of the module or entity/architecture to which
the vunit is bound. If omitted, the vunit binds to the top-level design unit of the design under
verification.
– The default clock declaration for the vunit.
– Any number of verification directives or PSL statements.
The following restrictions exist when providing assertions in a separate file.
Vunits can be bound only to a module, entity, or architecture.
The PSL file and its corresponding HDL file must be compiled together.
The following is an example using Verilog syntax that shows three assertions in one vunit.
vunit check_dram_controller(dram_control)
{
default clock = rose(clk);
// declare refresh sequence
sequence refresh_sequence = {
!cas_n && ras_n && we_n; [*1];
(!cas_n && !ras_n && we_n)[*2];
cas_n && ras_n};
sequence signal_refresh = {[*24]; rose(refresh)};
property refresh_rate = always {rose(reset_n) || rose(refresh)} |=>
{signal_refresh};
assert refresh_rate;
property check_refresh = always ({rose(refresh)} |->
{(mem_state != IDLE)[*0:14]; (mem_state == IDLE); refresh_sequence}
abort fell(reset_n));
assert check_refresh;