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ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-214 7 - Mixed-language simulation<br />

Verilog: instantiating SystemC<br />

SystemC instantiation criteria<br />

Exporting SystemC modules<br />

<strong>ModelSim</strong> <strong>SE</strong> User’s <strong>Manual</strong><br />

You can reference a SystemC module from Verilog as though the design unit is a module<br />

of the same name.<br />

A SystemC module can be instantiated in Verilog if it meets the following criteria:<br />

SystemC module names are case sensitive. The module name at the SystemC<br />

instantiation site must match exactly with the actual SystemC module name.<br />

SystemC modules are exported using the SC_MODULE_EXPORT macro. See<br />

"Exporting SystemC modules" (UM-214).<br />

The module ports are as listed in the table shown in "Channel <strong>and</strong> Port type mapping"<br />

(UM-196).<br />

Port data type mapping must match exactly. See the table in "Data type mapping" (UM-<br />

197).<br />

Port associations may be named or positional. Use the same port names <strong>and</strong> port positions<br />

that appear in the SystemC module declaration. Named port associations are case sensitive.<br />

Parameter support is available as of the <strong>ModelSim</strong> 6.0 release. See "Parameter support for<br />

Verilog instantiating SystemC" (UM-214).<br />

To be able to instantiate a SystemC module from Verilog (or use a SystemC module as a<br />

top level module), the module must be exported.<br />

Assume a SystemC module named transceiver exists, <strong>and</strong> that it is declared in header file<br />

transceiver.h. Then the module is exported by placing the following code in a .cpp file:<br />

#include "transceiver.h"<br />

SC_MODULE_EXPORT(transceiver);<br />

Parameter support for Verilog instantiating SystemC<br />

Passing parameters from Verilog to SystemC<br />

To pass actual parameter values, simply use the native Verilog parameter override syntax.<br />

Parameters are passed to SystemC via the module instance parameter value list.<br />

In addition to int, real, <strong>and</strong> string, <strong>ModelSim</strong> supports parameters with a bit range.<br />

Named parameter association must be used for all Verilog modules that instantiate<br />

SystemC.<br />

Retrieving parameter values<br />

To retrieve parameter override information from Verilog, you can use the following<br />

functions:<br />

void sc_get_param(const char* param_name, int& param_value);<br />

void sc_get_param(const char* param_name, double& param_value);<br />

void sc_get_param(const char* param_name, sc_string& param_value, char

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