ModelSim SE User's Manual - Electrical and Computer Engineering

UM-126 5 - Verilog simulation
Enabling design object visibility with the +acc option
ModelSim SE User’s Manual
Some of the optimizations performed by vopt impact design visibility to both the user
interface and the PLI routines. Many of the nets, ports, and registers are unavailable by
name in user interface commands and in the various graphic interface windows. In addition,
many of these objects do not have PLI Access handles, potentially affecting the operation
of PLI applications. However, a handle is guaranteed to exist for any object that is an
argument to a system task or function.
In the early stages of design, you may use one or more +acc options in conjunction with
vopt to enable access to specific design objects. Or, use the Visibility tab in the "Start
Simulation dialog" (GR-76).
Keep in mind that enabling design object access may reduce simulation performance.
The syntax for the +acc option is as follows:
+acc[=][+[.]]
is one or more of the following characters:
Meaning
b Enable access to individual bits of vector nets. This is necessary
for PLI applications that require handles to individual bits of
vector nets. Also, some user interface commands require this
access if you need to operate on net bits.
c Enable access to library cells. By default any Verilog module
that contains a non-empty specify block may be optimized, and
debug and PLI access may be limited. This option keeps module
cell visibility.
l Enable line number directives and process names for line
debugging, profiling, and code coverage.
n Enable access to nets.
p Enable access to ports. This disables the module inlining
optimization, and should be used for PLI applications that
require access to port handles, or for debugging (see below).
r Enable access to registers (including memories, integer,
time, and real types).
s Enable access to system tasks.
t Enable access to tasks and functions.
If is omitted, then access is enabled for all objects.
is a module name, optionally followed by "." to indicate all children of the
module. Multiple modules are allowed, each separated by a "+". If no modules are
specified, then all modules are affected. We strongly recommend specifying modules when
using +acc. Doing so will lessen the impact on performance.