ModelSim SE User's Manual - Electrical and Computer Engineering

Optimizing Verilog designs UM-127
If your design uses PLI applications that look for object handles in the design hierarchy,
then it is likely that you will need to use the +acc option. For example, the built-in
$dumpvars system task is an internal PLI application that requires handles to nets and
registers so that it can call the PLI routine acc_vcl_add() to monitor changes and dump the
values to a VCD file. This requires that access is enabled for the nets and registers on which
it operates. Suppose you want to dump all nets and registers in the entire design, and that
you have the following $dumpvars call in your testbench (no arguments to $dumpvars
means to dump everything in the entire design):
initial $dumpvars;
Then you need to optimize your design as follows to enable net and register access for all
modules in the design:
% vopt +acc=rn testbench
Optimizing gate-level designs
As another example, suppose you only need to dump nets and registers of a particular
instance in the design (the first argument of 1 means to dump just the variables in the
instance specified by the second argument):
initial $dumpvars(1, testbench.u1);
Then you need to compile your design as follows (assuming testbench.u1 refers to the
module design):
% vopt +acc=rn+design testbench
Finally, suppose you need to dump everything in the children instances of testbench.u1 (the
first argument of 0 means to also include all children of the instance):
initial $dumpvars(0, testbench.u1);
Then you need to compile your design as follows:
% vopt +acc=rn+design. testbench
To gain maximum performance, it may be necessary to enable the minimum required
access within the design.
Gate-level designs should not be optimized with vopt. These designs often have large
netlists that are slow to optimize with vopt. In most cases we recommend the following
flow for optimizing gate-level designs:
Compile the cell library using -fast. If the cell library is vendor supplied and the compiled
results will be placed in a read-only location, you should also use the -forcecode
argument along with -fast. The -forcecode argument ensures that code is generated for
inlined modules.
Compile the device under test and testbench without -fast.
There are two cases where you should not follow this flow:
If your testbench has hierarchical references into the cell library, optimizing the library
alone would result in unresolved references.
If you are passing parameters to the cell library from either the testbench or the design
under test.
ModelSim SE User’s Manual