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ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-84 4 - VHDL simulation<br />

Modifying stimulus<br />

Using with the PLI or FLI<br />

Syntax<br />

<strong>ModelSim</strong> <strong>SE</strong> User’s <strong>Manual</strong><br />

A primary use of elaboration files is repeatedly simulating the same design with different<br />

stimulus. The following mechanisms allow you to modify stimulus for each run.<br />

Use of the change comm<strong>and</strong> to modify parameters or generic values. This affects values<br />

only; it has no effect on triggers, compiler directives, or generate statements that<br />

reference either a generic or parameter.<br />

Use of the -filemap_elab = argument to establish a<br />

map between files named in the elaboration file. The file name, if it<br />

appears in the design as a file name (for example, a VHDL FILE object as well as some<br />

Verilog sysfuncs that take file names), is substituted with the file<br />

name. This mapping occurs before environment variable expansion <strong>and</strong> can’t be used to<br />

redirect stdin/stdout.<br />

VCD stimulus files can be specified when y ou load the elaboration file. Both vcdread <strong>and</strong><br />

vcdstim are supported. Specifying a different VCD file when you load the elaboration file<br />

supersedes a stimulus file you specify when you create the elaboration file.<br />

In Verilog, the use of +args which are readable by the PLI routine mc_scan_plusargs().<br />

+args values specified when you create the elaboration file are superseded by +args<br />

values specified when you load the elaboration file.<br />

PLI models do not require special code to function with an elaboration file as long as the<br />

model doesn't create simulation objects in its st<strong>and</strong>ard tf routines. The sizetf, misctf <strong>and</strong><br />

checktf calls that occur during elaboration are played back at -load_elab to ensure the PLI<br />

model is in the correct simulation state. Registered user tf routines called from the Verilog<br />

HDL will not occur until -load_elab is complete <strong>and</strong> the PLI model's state is restored.<br />

By default, FLI models are activated for checkpoint during elaboration file creation <strong>and</strong> are<br />

activated for restore during elaboration file load. (See the "Using checkpoint/restore with<br />

the FLI" section of the FLI Reference manual for more information.) FLI models that<br />

support checkpoint/restore will function correctly with elaboration files.<br />

FLI models that don't support checkpoint/restore may work if simulated with the<br />

-elab_defer_fli argument. When used in t<strong>and</strong>em with -elab, -elab_defer_fli defers calls to<br />

the FLI model's initialization function until elaboration file load time. Deferring FLI<br />

initialization skips the FLI checkpoint/restore activity (callbacks, mti_IsRestore(), ...) <strong>and</strong><br />

may allow these models to simulate correctly. However, deferring FLI initialization also<br />

causes FLI models in the design to be initialized in order with the entire design loaded. FLI<br />

models that are sensitive to this ordering may still not work correctly even if you use<br />

-elab_defer_fli.<br />

See the vsim comm<strong>and</strong> (CR-373) for details on -elab, -elab_cont, -elab_defer_fli,<br />

-compress_elab, -filemap_elab, <strong>and</strong> -load_elab.

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