ModelSim SE User's Manual - Electrical and Computer Engineering

SystemC: instantiating Verilog
Verilog instantiation criteria
SystemC: instantiating Verilog UM-209
To instantiate Verilog modules into a SystemC design, you must first create a "SystemC
foreign module declaration" (UM-209) for each Verilog module. Once you have created the
foreign module declaration, you can instantiate the foreign module just like any other
SystemC module.
A Verilog design unit may be instantiated within SystemC if it meets the following criteria:
The design unit is a module (UDPs and Verilog primitives are not allowed).
The ports are named ports (Verilog allows unnamed ports).
The Verilog module name must be a valid C++ identifier.
The ports are not connected to bidirectional pass switches (it is not possible to handle pass
switches in SystemC).
A Verilog module that is compiled into a library can be instantiated in a SystemC design as
though the module were a SystemC module by passing the Verilog module name to the
foreign module constructor. For an illustration of this, see "Example #1" (UM-210).
SystemC and Verilog identifiers
The SystemC identifiers for the module name and port names are the same as the Verilog
identifiers for the module name and port names. Verilog identifiers must be valid C++
identifiers. SystemC and Verilog are both case sensitive.
SystemC foreign module declaration
In cases where you want to run a mixed simulation with SystemC and Verilog, you must
generate and declare a foreign module that stands in for each Verilog module instantiated
under SystemC. The foreign modules can be created in one of two ways:
running scgenmod, a utility that automatically generates your foreign module declaration
(much like vgencomp generates a component declaration)
modifying your SystemC source code manually
Using scgenmod
After you have analyzed the design, you can generate a foreign module declaration with an
scgenmod command (CR-258) similar to the following:
scgenmod mod1
where mod1 is a Verilog module. A foreign module declaration for the specified module is
written to stdout.
ModelSim SE User’s Manual