ModelSim SE User's Manual - Electrical and Computer Engineering

UM-434 17 - Signal Spy
$signal_force
Syntax
Returns
Arguments
ModelSim SE User’s Manual
The $signal_force() system task forces the value specified onto an existing VHDL signal
or Verilog register/net (called the dest_object). This allows you to force signals, registers,
or nets at any level of the design hierarchy from within a Verilog module (e.g., a testbench).
A $signal_force works the same as the force command (CR-180) with the exception that you
cannot issue a repeating force. The force will remain on the signal until a $signal_release,
a force or release command, or a subsequent $signal_force is issued. $signal_force can be
called concurrently or sequentially in a process.
$signal_force( dest_object, value, rel_time, force_type, cancel_period,
verbose )
Nothing
Name Type Description
dest_object string Required. A full hierarchical path (or relative
path with reference to the calling block) to an
existing VHDL signal or Verilog register/net.
Use the path separator to which your
simulation is set (i.e., "/" or "."). A full
hierarchical path must begin with a "/" or ".".
The path must be contained within double
quotes.
value string Required. Specifies the value to which the
dest_object is to be forced. The specified
value must be appropriate for the type.
rel_time integer, real, or
time
Optional. Specifies a time relative to the
current simulation time for the force to occur.
The default is 0.
force_type integer Optional. Specifies the type of force that will
be applied. The value must be one of the
following; 0 (default), 1 (deposit), 2 (drive),
or 3 (freeze). The default is "default" (which is
"freeze" for unresolved objects or "drive" for
resolved objects). See the force command
(CR-180) for further details on force type.