ModelSim SE User's Manual - Electrical and Computer Engineering

UM-64 3 - Design libraries
Specifying the resource libraries
Verilog resource libraries
VHDL resource libraries
Predefined libraries
ModelSim SE User’s Manual
ModelSim supports separate compilation of distinct portions of a Verilog design. The vlog
(CR-358) compiler is used to compile one or more source files into a specified library. The
library thus contains pre-compiled modules and UDPs that are referenced by the simulator
as it loads the design.
Important: Resource libraries are specified differently for Verilog and VHDL. For
Verilog you use either the -L or -Lf argument to vlog (CR-358). See "Library usage" (UM-
117) for more information.
Within a VHDL source file, you use the VHDL library clause to specify logical names of
one or more resource libraries to be referenced in the subsequent design unit. The scope of
a library clause includes the text region that starts immediately after the library clause and
extends to the end of the declarative region of the associated design unit. It does not extend
to the next design unit in the file.
Note that the library clause is not used to specify the working library into which the design
unit is placed after compilation. The vcom command (CR-311) adds compiled design units
to the current working library. By default, this is the library named work. To change the
current working library, you can use vcom -work and specify the name of the desired target
library.
Certain resource libraries are predefined in standard VHDL. The library named std
contains the packages standard and textio, which should not be modified. The contents of
these packages and other aspects of the predefined language environment are documented
in the IEEE Standard VHDL Language Reference Manual, Std 1076. See also, "Using the
TextIO package" (UM-88).
A VHDL use clause can be specified to select particular declarations in a library or package
that are to be visible within a design unit during compilation. A use clause references the
compiled version of the package—not the source.
By default, every VHDL design unit is assumed to contain the following declarations:
LIBRARY std, work;
USE std.standard.all
To specify that all declarations in a library or package can be referenced, add the suffix .all
to the library/package name. For example, the use clause above specifies that all
declarations in the package standard, in the design library named std, are to be visible to
the VHDL design unit immediately following the use clause. Other libraries or packages
are not visible unless they are explicitly specified using a library or use clause.
Another predefined library is work, the library where a design unit is stored after it is
compiled as described earlier. There is no limit to the number of libraries that can be
referenced, but only one library is modified during compilation.