ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-184 6 - SystemC simulation Troubleshooting SystemC errors ModelSim SE User’s Manual In the process of modifying your SystemC design to run on ModelSim, you may encounter several common errors. This section highlights some actions you can take to correct such errors. Unexplained behaviors during loading or runtime Errors during loading If your SystemC simulation behaves in otherwise unexplainable ways, you should determine whether you need to adjust the stack space ModelSim allocates for threads in your design. The required size for a stack depends on the depth of functions on that stack and the number of bytes they require for automatic (local) variables. By default, the SystemC stack size is 10,000 bytes per thread. You may have one or more threads needing a larger stack size. If so, call the SystemC function set_stack_size() and adjust the stack to accommodate your needs. Note that you can ask for too much stack space and have unexplained behavior as well. When simulating your SystemC design, you might get a "failed to load sc lib" message because of an undefined symbol, looking something like this: # Loading /home/cmg/newport2_systemc/chip/vhdl/work/systemc.so # ** Error: (vsim-3197) Load of "/home/cmg/newport2_systemc/chip/vhdl/work/ systemc.so" failed: ld.so.1: /home/icds_nut/modelsim/5.8a/sunos5/vsimk: fatal: relocation error: file /home/cmg/newport2_systemc/chip/vhdl/work/systemc.so: symbol _Z28host_respond_to_vhdl_requestPm: referenced symbol not found. # ** Error: (vsim-3676) Could not load shared library /home/cmg/ newport2_systemc/chip/vhdl/work/systemc.so for SystemC module 'host_xtor'. Source of undefined symbol message The causes for such an error could be: missing definition missing type bad link order specified in sccom -link multiply-defined symbols Missing definition If the undefined symbol is a C function in your code or a library you are linking with, be sure that you declared it as an extern "C" function: extern "C" void myFunc();
Troubleshooting SystemC errors UM-185 This should appear in any header files include in your C++ sources compiled by sccom. It tells the compiler to expect a regular C function; otherwise the compiler decorates the name for C++ and then the symbol can't be found. Also, be sure that you actually linked with an object file that fully defines the symbol. You can use the "nm" utility on Unix platforms to test your SystemC object files and any libraries you link with your SystemC sources. For example, assume you ran the following commands: sccom test.cpp sccom -link libSupport.a If there is an unresolved symbol and it is not defined in your sources, it should be correctly defined in any linked libraries: nm libSupport.a | grep "mySymbol" Missing type When you get errors during design elaboration, be sure that all the items in your SystemC design hierarchy, including parent elements, are declared in the declarative region of a module. If not, sccom ignores them. For example, we have a design containing SystemC over VHDL. The following declaration of a child module "test" inside the constructor module of the code is not allowed and will produce an error: SC_MODULE(Export) { SC_CTOR(Export) { test *testInst; testInst = new test("test"); } }; The error results from the fact that the SystemC parse operation will not see any of the children of "test". Nor will any debug information be attached to it. Thus, the signal has no type information and can not be bound to the VHDL port. The solution is to move the element declaration into the declarative region of the module. Misplaced "-link" option The order in which you place the -link option within the sccom -link command is critical. There is a big difference between the following two commands: and sccom -link liblocal.a sccom liblocal.a -link The first command ensures that your SystemC object files are seen by the linker before the library "liblocal.a" and the second command ensures that "liblocal.a" is seen first. Some linkers can look for undefined symbols in libraries that follow the undefined reference while others can look both ways. For more information on command syntax and dependencies, see sccom (CR-254). ModelSim SE User’s Manual
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ModelSim® Advanced Verification an
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Table of Contents 1 - Introduction
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Delta delays . . . . . . . . . . .
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ModelSim Verilog system tasks and f
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VHDL: instantiating SystemC . . . .
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Creating waveforms from patterns .
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14 - PSL Assertions (UM-359) What a
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17 - Signal Spy (UM-417) Introducti
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Starting the debugger . . . . . . .
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Steps in flow . . . . . . . . . . .
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1 - Introduction Chapter contents M
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ModelSim simulation task overview M
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Basic steps for simulation UM-25 Li
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ModelSim modes of operation ModelSi
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ModelSim graphic interface overview
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Sections in this document Sections
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Sections in this document UM-33 H -
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Where to find our documentation Whe
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2 - Projects Chapter contents Intro
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Project conversion between versions
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workspace Getting started with proj
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Step 3 — Compiling the files Gett
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The Project tab Sorting the list Th
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Grouping files Changing compile ord
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Optimization Configurations Creatin
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Organizing projects with folders UM
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Specifying file properties and proj
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Accessing projects from the command
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3 - Design libraries Chapter conten
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Archives Design library overview UM
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Managing library contents Working w
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Moving a library Working with desig
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Alternate IEEE libraries supplied R
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Referencing source files with locat
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Importing FPGA libraries Importing
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4 - VHDL simulation Chapter content
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Compiling VHDL files Creating a des
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Differences between language versio
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Compiling VHDL files UM-77 bit stri
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Default binding Simulating VHDL des
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Simulating VHDL designs UM-81 In th
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Creating an elaboration file Loadin
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Example Simulating with an elaborat
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Controlling checkpoint file compres
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Using STD_INPUT and STD_OUTPUT with
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Reading and writing hexadecimal num
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VITAL specification and source code
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Compiling and simulating with accel
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init_signal_driver() init_signal_sp
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to_time() Util package UM-99 to_tim
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Modeling memory ’87 and ’93 exa
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if (mwrite = '1') then ram(address)
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BEGIN return mem(to_integer(addr));
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BEGIN FOR i IN 0 TO 1023 LOOP we
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Converting an integer into a bit_ve
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5 - Verilog simulation Chapter cont
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Introduction ModelSim Verilog basic
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Incremental compilation Compiling V
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Library usage Compiling Verilog fil
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Verilog-XL compatible compiler argu
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Compiling Verilog files UM-121 The
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Verilog generate statements Compili
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Naming the optimized design Optimiz
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Optimizing Verilog designs UM-127 I
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Simulating Verilog designs Simulato
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`timescale, -t, and rounding Simula
Page 133 and 134: Simulating Verilog designs UM-133 T
Page 135 and 136: Simulating Verilog designs UM-135 M
Page 137 and 138: +pulse_e_style_onevent +pulse_int_e
Page 139 and 140: Creating an elaboration file Loadin
Page 141 and 142: Example Simulating with an elaborat
Page 143 and 144: Controlling checkpoint file compres
Page 145 and 146: Distributed delay mode In distribut
Page 147 and 148: System tasks and functions UM-147 a
Page 149 and 150: File I/O tasks $fclose $fopen $fwri
Page 151 and 152: System tasks and functions UM-151 T
Page 153 and 154: Compiler directives Compiler direct
Page 155 and 156: ModelSim compiler directives The fo
Page 157 and 158: Determining which memories were imp
Page 159 and 160: 6 - SystemC simulation Chapter cont
Page 161 and 162: Supported platforms and compiler ve
Page 163 and 164: Usage flow for SystemC-only designs
Page 165 and 166: Code modification examples Compilin
Page 167 and 168: Example 3 Compiling SystemC files U
Page 169 and 170: Restrictions on compiling with HP a
Page 171 and 172: Issues with C++ templates Templatiz
Page 173 and 174: Simulating SystemC designs Loading
Page 175 and 176: Initialization and cleanup of Syste
Page 177 and 178: Waveform compare Debugging the desi
Page 179 and 180: Debugging the design UM-179 The gdb
Page 181 and 182: Viewing FIFOs SystemC object and ty
Page 183: OSCI 2.1 features supported Differe
Page 187 and 188: 7 - Mixed-language simulation Chapt
Page 189 and 190: Usage flow for mixed-language simul
Page 191 and 192: Simulator resolution limit Runtime
Page 193 and 194: Mapping data types Verilog to VHDL
Page 195 and 196: VHDL to Verilog mappings Mapping da
Page 197 and 198: Channels Ports Verilog mapping sc_b
Page 199 and 200: Verilog sc_logic sc_bit bool SuX 'X
Page 201 and 202: SystemC VHDL sc_int, sc_uint bit_ve
Page 203 and 204: VHDL: instantiating Verilog Verilog
Page 205 and 206: The generic type is determined by t
Page 207 and 208: Verilog: instantiating VHDL VHDL in
Page 209 and 210: SystemC: instantiating Verilog Veri
Page 211 and 212: Example #2 SystemC: instantiating V
Page 213 and 214: }; } #endif // Connect ports chip->
Page 215 and 216: Example of parameter use format_cha
Page 217 and 218: SystemC: instantiating VHDL VHDL in
Page 219 and 220: Example SystemC: instantiating VHDL
Page 221 and 222: ); END ringbuf; ARCHITECTURE RTL OF
Page 223 and 224: vgencomp component declaration vgen
Page 225 and 226: 8 - WLF files (datasets) and virtua
Page 227 and 228: Saving a simulation to a WLF file O
Page 229 and 230: Managing multiple datasets WLF file
Page 231 and 232: Saving at intervals with Dataset Sn
Page 233 and 234: Virtual Objects (User-defined buses
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Virtual regions Virtual types Virtu
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9 - Waveform analysis Chapter conte
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Introduction Objects you can view W
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Wave window overview UM-241 Here is
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List window overview List window ov
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Measuring time with cursors in the
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Jumping to a signal transition Meas
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Zooming the Wave window display Zoo
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Searching in the Wave and List wind
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Using the Expression Builder for ex
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Formatting the Wave window Setting
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Formatting the Wave window UM-257 3
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Formatting the List window Setting
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Saving the window format Saving the
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Saving List window data to a file S
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Configuring new line triggering in
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Configuring new line triggering in
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Miscellaneous tasks Examining wavef
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Comparison Wizard Waveform Compare
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Test Dataset Waveform Compare UM-27
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Adding regions Waveform Compare UM-
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Clocked comparison Waveform Compare
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Viewing differences in the Wave win
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Compare icons Waveform Compare UM-2
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Comparing hierarchical and flattene
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10 - Generating stimulus with Wavef
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Getting started You can use Wavefor
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Creating waveforms from patterns Cr
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Editing waveforms GR-291 These comm
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Simulating directly from waveform e
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Driving simulation with the saved s
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Saving the waveform editor commands
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11 - Tracing signals with the Dataf
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Adding objects to the window Adding
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Exploring the connectivity of your
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Zooming and panning Zooming with to
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Tracing the source of an unknown (X
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Finding objects by name in the Data
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Printing on Windows platforms Selec
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Symbol mapping Symbol mapping UM-31
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Configuring window options Configur
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12 - Profiling performance and memo
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Getting started Memory allocation p
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Enabling the statistical sampling p
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Interpreting profiler data Interpre
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The Call Tree view Viewing profiler
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Viewing profile details Viewing pro
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Integration with Source windows Int
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Reporting profiler results Reportin
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13 - Measuring code coverage Chapte
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Supported types ModelSim code cover
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Enabling code coverage Enabling cod
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Enabling code coverage UM-339 Next,
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Viewing coverage data in the Source
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Toggle coverage Enabling Toggle cov
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3 Produce the report with the toggl
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Excluding objects from coverage Exc
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end instance Default filter file Ex
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XML output Reporting coverage data
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Instance report with line details R
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Coverage statistics details Conditi
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Coverage statistics details UM-357
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14 - PSL Assertions Chapter content
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PSL assertion language What are ass
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Using cover directives Using assert
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REF2); signal mem_state : memory_st
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} // Check the write cycle property
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Multi-clocked properties and defaul
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Using endpoints in HDL code Example
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Restrictions Clocking endpoints Usi
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Compiling and simulating assertions
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Enabling/disabling failure and pass
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Setting failure and pass limits Man
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Reporting on assertions Reporting o
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15 - Functional coverage with PSL a
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Compiling and simulating functional
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Weighting coverage directives Confi
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Viewing coverage directives in the
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Reporting functional coverage stati
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Tag Meaning Understanding aggregate
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Saving functional coverage data Sav
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Clearing functional coverage data C
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16 - C Debug Chapter contents Intro
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Supported platforms and gdb version
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Setting breakpoints Setting breakpo
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Stepping in C Debug Stepping in C D
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Identifying all registered function
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Auto find bp versus Auto step mode
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Debugging functions during elaborat
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VPI functions in initialization mod
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C Debug command reference C Debug c
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17 - Signal Spy Chapter contents In
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init_signal_driver Call only once S
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Example library IEEE, modelsim_lib;
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Arguments Related procedures Limita
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signal_force Syntax Returns Argumen
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signal_release Syntax Returns Argum
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$init_signal_driver Call only once
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Example `timescale 1 ps / 1 ps modu
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Related tasks Limitations Example N
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Related tasks Limitations Example N
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Example module testbench; reg relea
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18 - Standard Delay Format (SDF) Ti
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SDF specification with the GUI Erro
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Resolving errors VHDL VITAL SDF UM-
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Examples Optional arguments can be
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REMOVAL is matched to $removal: SDF
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Optional conditions Timing check po
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Interconnect delays Interconnect de
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Mistaking a component or module nam
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19 - Value Change Dump (VCD) Files
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Checkpoint/restore and writing VCD
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Example 3 — Mixed-HDL design Firs
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ModelSim VCD commands and VCD tasks
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A VCD file from source to output VH
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x) x* x+ x, $end #300 $dumpon 1! 0"
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Capturing port driver data Supporte
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Example VCD output from vcd dumppor
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20 - Tcl and macros (DO files) Chap
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Tcl commands Tcl commands UM-473 Fo
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Tcl command syntax UM-475 7 If a wo
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set command syntax Tcl command synt
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Variable substitution System comman
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ModelSim Tcl time commands Conversi
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Tcl examples This is an example of
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} if {$windowName == ""} { # Dialog
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Macros (DO files) Creating DO files
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set vFilesExist 1 } shift } if {$vh
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Using the Tcl source command with D
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The Tcl Debugger Starting the debug
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Breakpoints The Tcl Debugger UM-495
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TclPro Debugger TclPro Debugger UM-
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A - ModelSim GUI changes Appendix c
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Main window changes UM-501 See "Cus
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Main window changes UM-503 File > O
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View menu The View menu has been re
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Tools menu The 6.0 Main window Tool
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List window changes File menu The L
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File menu See "Memory windows" (GR-
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View menu The Memory window > View
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Edit menu The Signals window > Edit
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View menu The Source window > File
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B - ModelSim variables Appendix con
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Environment variables Environment v
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Library mapping with environment va
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[Library] library path variables Va
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[vcom] VHDL compiler control variab
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[vsim] simulator control variables
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Preference variables located in INI
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Commonly used INI variables Prefere
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Force command defaults Preference v
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Variable precedence Variable preced
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Special considerations for the now
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C - Error and warning messages Appe
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ModelSim message system UM-547 Ther
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Exit codes The table below describe
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Miscellaneous messages Miscellaneou
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Miscellaneous messages UM-553 model
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VSIM license lost Message text Cons
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Suggested action Multiply defined s
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D - Verilog PLI / VPI / DPI Chapter
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Registering PLI applications Regist
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Registering VPI applications Exampl
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Registering DPI applications Regist
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For Windows only: Run a preliminary
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32-bit Linux platform Compiling and
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gcc compiler gcc -c -I//modeltech/i
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For DPI imports 64-bit IBM RS/6000
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32-bit Linux platform Compiling and
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64-bit Solaris platform Compiling a
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64-bit IBM RS/6000 platform DPI spe
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Loading shared objects with global
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VPI example The following example i
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The PLI callback reason argument Th
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The sizetf callback function The si
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Third party PLI applications Third
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IEEE Std 1364 ACC routines IEEE Std
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IEEE Std 1364 TF routines IEEE Std
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SystemVerilog DPI access routines S
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Verilog-XL compatible routines Veri
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PLI/VPI tracing The purpose of trac
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Debugging PLI/VPI/DPI application c
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E - ModelSim shortcuts Appendix con
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Main and Source window mouse and ke
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Keystrokes - UNIX Keystrokes - Wind
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Wave window mouse and keyboard shor
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F - System initialization Appendix
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Environment variables accessed duri
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Initialization sequence Initializat
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G - Logic Modeling SmartModels Appe
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Creating foreign architectures with
Page 621 and 622:
Vector ports Entity details VHDL Sm
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SmartModel Windows VHDL SmartModel
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Verilog SmartModel interface Verilo
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H - Logic Modeling hardware models
Page 629 and 630:
Creating foreign architectures with
Page 631 and 632:
Vector ports Architecture details V
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End-User License Agreement IMPORTAN
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COMPLIED WITH THIS AGREEMENT. MENTO
Page 637 and 638:
Graphics shall only use or disclose
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Index CR = Command Reference, UM =
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Stop on quit mode UM-414 C Debug se
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mem search CR-204 modelsim CR-206 n
Page 645 and 646:
ange checking in VHDL CR-316, UM-74
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Add Folder GR-47 C Debug setup GR-9
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F -f CR-360 F8 function key UM-607
Page 651 and 652:
Verilog modules UM-125 VHDL subprog
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Memory window GR-169 GUI changes UM
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optimizing Verilog designs design o
Page 657 and 658:
eaders and drivers UM-303 readers c
Page 659 and 660:
adix specifying for examine CR-163
Page 661 and 662:
system tasks VCD UM-461 Verilog UM-
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U -u CR-365 unbound component GR-53
Page 665 and 666:
library clause UM-64 mixed designs
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text editing UM-605 windows Active
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