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ModelSim SE User's Manual - Electrical and Computer Engineering

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UM-136 5 - Verilog simulation<br />

Negative timing check limits<br />

<strong>ModelSim</strong> <strong>SE</strong> User’s <strong>Manual</strong><br />

Verilog supports negative limit values in the $setuphold <strong>and</strong> $recrem system tasks. These<br />

tasks have optional delayed versions of input signals to insure proper evaluation of models<br />

with negative timing check limits. Delay values for these delayed nets are determined by<br />

the simulator so that valid data is available for evaluation before a clocking signal.<br />

Example<br />

$setuphold(posedge clk, negedge d, 5, -3, Notifier,,, clk_dly, d_dly);<br />

d violation 5<br />

region<br />

clk<br />

<strong>ModelSim</strong> calculates the delay for signal d_dly as 4 time units instead of 3. It does this to<br />

prevent d_dly <strong>and</strong> clk_dly from occurring simultaneously when a violation isn’t reported.<br />

<strong>ModelSim</strong> accepts negative limit checks by default, unlike current versions of Verilog-XL.<br />

To match Verilog-XL default behavior (i.e., zeroing all negative timing check limits), use<br />

the +no_neg_tcheck argument to vsim (CR-373).<br />

Negative timing constraint algorithm<br />

The algorithm <strong>ModelSim</strong> uses to calculate delays for delayed nets isn’t described in IEEE<br />

Std 1364. Rather, <strong>ModelSim</strong> matches Verilog-XL behavior. The algorithm attempts to find<br />

a set of delays so the data net is valid when the clock net transitions <strong>and</strong> the timing checks<br />

are satisfied. The algorithm is iterative because a set of delays can be selected that satisfies<br />

all timing checks for a pair of inputs but then causes mis-ordering of another pair (where<br />

both pairs of inputs share a common input). When a set of delays that satisfies all timing<br />

checks is found, the delays are said to converge.<br />

Verilog-XL compatible simulator arguments<br />

The simulator arguments listed below are equivalent to Verilog-XL arguments <strong>and</strong> may<br />

ease the porting of a design to <strong>ModelSim</strong>. See the vsim comm<strong>and</strong> (CR-373) for a description<br />

of each argument.<br />

+alt_path_delays<br />

-l <br />

+maxdelays<br />

+mindelays<br />

+multisource_int_delays<br />

+no_cancelled_e_msg<br />

+no_neg_tchk<br />

+no_notifier<br />

+no_path_edge<br />

+no_pulse_msg<br />

-no_risefall_delaynets<br />

+no_show_cancelled_e<br />

+nosdfwarn<br />

+nowarn<br />

+ntc_warn<br />

+pulse_e/<br />

+pulse_e_style_ondetect<br />

3<br />

0

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