ModelSim SE User's Manual - Electrical and Computer Engineering

UM-190 7 - Mixed-language simulation
Separate compilers, common design libraries
ModelSim SE User’s Manual
VHDL source code is compiled by vcom (CR-311) and the resulting compiled design units
(entities, architectures, configurations, and packages) are stored in the working library.
Likewise, Verilog source code is compiled by vlog (CR-358) and the resulting design units
(modules and UDPs) are stored in the working library.
SystemC/C++ source code is compiled with the sccom command (CR-254). The resulting
object code is compiled into the working library.
Design libraries can store any combination of design units from any of the supported
languages, provided the design unit names do not overlap (VHDL design unit names are
changed to lower case). See "Design libraries" (UM-57) for more information about library
management.
Access limitations in mixed-language designs
Optimizing mixed designs
The Verilog language allows hierarchical access to objects throughout the design. This is
not the case with VHDL or SystemC. You cannot directly read or change a VHDL or
SystemC object (signal, variable, generic, etc.) with a hierarchical reference within a
mixed-language design. Furthermore, you cannot directly access a Verilog object up or
down the hierarchy if there is an interceding VHDL or SystemC block.
You have two options for accessing VHDL objects or Verilog objects "obstructed" by an
interceding block: 1) propagate the value through the ports of all design units in the
hierarchy; 2) use the Signal Spy procedures or system tasks (see Chapter 17 - Signal Spy
for details).
To access obstructed SystemC objects, propagate the value through the ports of all design
units in the hierarchy or use the control/observe functions (see "Hierarchical references in
mixed HDL/SystemC designs" (UM-192).
The vopt command (CR-371) performs global optimizations to improve simulator
performance. In the current release, vopt primarily optimizes Verilog design units. See
"Optimizing Verilog designs" (UM-124) for further details.