ModelSim SE User's Manual - Electrical and Computer Engineering

Comparing hierarchical and flattened designs
Waveform Compare UM-283
If you are comparing a hierarchical RTL design simulation against a flattened synthesized
design simulation, you may have different hierarchies, different signal names, and the
buses may be broken down into one-bit signals in the gate-level design. All of these
differences can be handled by ModelSim’s Waveform Compare feature.
If the test design is hierarchical but the hierarchy is different from the hierarchy of the
reference design, you can use the compare add command (CR-94) to specify which
region path in the test design corresponds to that in the reference design.
If the test design is flattened and test signal names are different from reference signal
names, the compare add command (CR-94) allows you to specify which signal in the test
design will be compared to which signal in the reference design.
If, in addition, buses have been dismantled, or "bit-blasted", you can use the -rebuild
option of the compare add command (CR-94) to automatically rebuild the bus in the test
design. This will allow you to look at the differences as one bus versus another.
If signals in the RTL test design are different in type from the synthesized signals in the
reference design – registers versus nets, for example – the Waveform Compare feature will
automatically do the type conversion for you. If the type differences are too extreme (say
integer versus real), Waveform Compare will let you know.
ModelSim SE User’s Manual