ModelSim SE User's Manual - Electrical and Computer Engineering

UM-206 7 - Mixed-language simulation
Modules with unnamed ports
ModelSim SE User’s Manual
Verilog allows modules to have unnamed ports, whereas VHDL requires that all ports have
names. If any of the Verilog ports are unnamed, then all are considered to be unnamed, and
it is not possible to create a matching VHDL component. In such cases, the module may
not be instantiated from VHDL.
Unnamed ports occur when the module port list contains bit-selects, part-selects, or
concatenations, as in the following example:
module m(a[3:0], b[1], b[0], {c,d});
input [3:0] a;
input [1:0] b;
input c, d;
endmodule
Note that a[3:0] is considered to be unnamed even though it is a full part-select. A common
mistake is to include the vector bounds in the port list, which has the undesired side effect
of making the ports unnamed (which prevents the user from connecting by name even in
an all-Verilog design).
Most modules having unnamed ports can be easily rewritten to explicitly name the ports,
thus allowing the module to be instantiated from VHDL. Consider the following example:
module m(y[1], y[0], a[1], a[0]);
output [1:0] y;
input [1:0] a;
endmodule
Here is the same module rewritten with explicit port names added:
module m(.y1(y[1]), .y0(y[0]), .a1(a[1]), .a0(a[0]));
output [1:0] y;
input [1:0] a;
endmodule
"Empty" ports
Verilog modules may have "empty" ports, which are also unnamed, but they are treated
differently from other unnamed ports. If the only unnamed ports are "empty", then the other
ports may still be connected to by name, as in the following example:
module m(a, , b);
input a, b;
endmodule
Although this module has an empty port between ports "a" and "b", the named ports in the
module can still be connected to from VHDL.