ModelSim SE User's Manual - Electrical and Computer Engineering

init_signal_driver
Call only once
Syntax
Returns
init_signal_driver UM-419
The init_signal_driver() procedure drives the value of a VHDL signal or Verilog net (called
the src_object) onto an existing VHDL signal or Verilog net (called the dest_object). This
allows you to drive signals or nets at any level of the design hierarchy from within a VHDL
architecture (e.g., a testbench).
The init_signal_driver procedure drives the value onto the destination signal just as if the
signals were directly connected in the HDL code. Any existing or subsequent drive or force
of the destination signal, by some other means, will be considered with the
init_signal_driver value in the resolution of the signal.
The init_signal_driver procedure creates a persistent relationship between the source and
destination signals. Hence, you need to call init_signal_driver only once for a particular
pair of signals. Once init_signal_driver is called, any change on the source signal will be
driven on the destination signal until the end of the simulation.
Thus, we recommend that you place all init_signal_driver calls in a VHDL process. You
need to code the VHDL process correctly so that it is executed only once. The VHDL
process should not be sensitive to any signals and should contain only init_signal_driver
calls and a simple wait statement. The process will execute once and then wait forever. See
the example below.
Nothing
init_signal_driver(src_object, dest_object, delay, delay_type, verbose)
ModelSim SE User’s Manual