ModelSim SE User's Manual - Electrical and Computer Engineering

UM-362 14 - PSL Assertions
Using assertions in ModelSim
Assertion flow
Limitations
ModelSim SE User’s Manual
The following diagram gives a visual depiction of using assertions in ModelSim.
HDL with
embedded assertions
Wave
window
or HDL assertions file
vlog/vcom
vsim
Assertions
pane
vlog/vcom -pslfile
ModelSim lets you embed assertions within your Verilog or VHDL code or supply them in
a separate file. If the assertions are embedded, vlog/vcom will compile them automatically.
If the assertions are in a separate file, you add the -pslfile argument to vlog/vcom. Once
compilation is complete, you invoke the simulator vsim on the design. The simulator
automatically handles any assertions that are present in the design. From there you run the
simulation and debug any assertion failures.
The current release has some limitations. Most of these features will be added in future
releases.
Only the simple subset of PSL is supported.
Vunits cannot be bound to a design unit instance. They can be bound only to a module,
entity, and architecture.
There is no support for verification unit inheritance–vunits cannot be derived from other
vunits.
There is no support for unclocked assertions. Level-sensitive clock expressions are not
allowed.
There is no support for %for and %if preprocessor commands.
There is no support for integer, structures, and union in the modeling layer. The only PSL
built-in functions currently supported are rose(), fell(), and prev().