ModelSim SE User's Manual - Electrical and Computer Engineering

Simulating Verilog designs UM-133
The tables below show two of the many valid evaluations of these statements. Evaluation
events are denoted by a number where the number is the statement to be evaluated. Update
events are denoted (old->new) where indicates the reg being updated and
new is the updated value.
Table 1: Evaluation 1
Event being processed Active event queue
q(0 → 1) 1, 2
q(0 → 1)
1 p(0 → 1), 2
p(0 → 1) 3, 2
3 clk(0 → 1), 2
clk(0 → 1) 4, 2
4 2
2 p2(1 → 0)
p2(1 → 0) 3
3 clk(1 → 0)
clk(1 → 0)
Table 2: Evaluation 2
Event being processed Active event queue
q(0 → 1) 1, 2
q(0 → 1)
1 p(0 → 1), 2
2 p2(1 → 0), p(0 → 1)
p(0 → 1) 3, p2(1 → 0)
p2(1 → 0) 3
3 (clk doesn’t change)
Again, both evaluations are valid. However, in Evaluation 1, clk has a glitch on it; in
Evaluation 2, clk doesn’t. This indicates that the design has a zero-delay race condition on
clk.
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