ModelSim SE User's Manual - Electrical and Computer Engineering

Usage flow for mixed-language simulations
The usage flow for mixed-language designs is as follows:
Usage flow for mixed-language simulations UM-189
1 Analyze HDL source code using vcom (CR-311) or vlog (CR-358) and SystemC C++
source code using sccom (CR-254). Analyze all modules in the design following orderof-analysis
rules.
For SystemC designs with HDL instances:
Create a SystemC foreign module declaration for all Verilog and VHDL instances (see
"SystemC foreign module declaration" (UM-209) or (UM-217)).
For Verilog/VHDL designs with SystemC instances:
Export any SystemC instances that will be directly instantiated by Verilog/VHDL using
the SC_MODULE_EXPORT macro. Exported SystemC modules can be instantianted
just as you would instantiate any Verilog/VHDL module or design unit.
2 For designs containing SystemC:
Link all objects in the design using sccom (CR-254) -link.
3 If you have Verilog modules in your mixed design that you would like to optimize, you
would run the vopt command (CR-371) on the top-level design unit. See "Optimizing
mixed designs" (UM-190).
4 Simulate the design with the vsim command (CR-373).
5 Issue run (CR-252) commands from the ModelSim GUI.
6 Debug your design using ModelSim GUI features.
ModelSim SE User’s Manual