ModelSim SE User's Manual - Electrical and Computer Engineering

G - Logic Modeling SmartModels
Appendix contents
VHDL SmartModel interface . . . . . . . . . . . UM-618
Creating foreign architectures with sm_entity . . . . . UM-619
Vector ports . . . . . . . . . . . . . . UM-621
Command channel. . . . . . . . . . . . . UM-622
SmartModel Windows . . . . . . . . . . . UM-623
Memory arrays . . . . . . . . . . . . . UM-624
Verilog SmartModel interface . . . . . . . . . . . UM-625
Linking the LMTV interface to the simulator. . . . . . UM-625
The Logic Modeling SWIFT-based SmartModel library can be used with ModelSim VHDL and
Verilog. The SmartModel library is a collection of behavioral models supplied in binary form
with a procedural interface that is accessed by the simulator. This appendix describes how to
use the SmartModel library with ModelSim.
The SmartModel library must be obtained from Logic Modeling along with the
documentation that describes how to use it. This appendix only describes the specifics of
using the library with ModelSim.
A 32-bit SmartModel will not run with a 64-bit version of SE. When trying to load the
operating system specific 32-bit library into the 64-bit executable, the pointer sizes will be
incorrect.
UM-617
ModelSim SE User’s Manual