MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
The second step is to either read or write configuration data into the
CONFIG_DATA register. If the CONFIG_ADDRESS register is set up
correctly, the PHB will pass this access on to the PCI bus as a configuration
cycle.
The addresses of the CONFIG_ADDRESS and CONFIG_DATA registers
are actually embedded within PCI I/O space. If the CONFIG_ADDRESS
register has been set incorrectly or the access to either the
CONFIG_ADDRESS or CONFIG_DATA register is not 1, 2, or 4 bytes
wide, the PHB will pass the access on to PCI as a normal I/O Space
transfer.
The CONFIG_ADDRESS register is located at offset $CF8 from the
bottom of PCI I/O space. The CONFIG_DATA register is located at offset
$CFC from the bottom of PCI I/O space. The PHB address decode logic
has been designed such that XSADD3 and XSOFF3 must be used for
mapping to PCI Configuration (consequently I/O) space. The
XSADD3/XSOFF3 register group is initialized at reset to allow PCI I/O
access starting at address $80000000. The powerup location (Little Endian
disabled) of the CONFIG_ADDRESS register is $80000CF8, and the
CONFIG_DATA register is located at $80000CFC.
The CONFIG_ADDRESS register must be prefilled with four fields: the
Register Number, the Function Number, the Device Number, and the Bus
Number.
The Register Number and the Function Number get passed along to the
PCI bus as a portion of the lower address bits.
When performing a configuration cycle, the PHB uses the upper 20
address bits as IDSEL lines. During the address phase of a configuration
cycle, only one of the upper address bits will be set.
2-32 Computer Group Literature Center Web Site