MVME5100 Single Board Computer Programmer's Reference Guide

I 2 C Current Address Read
Functional Description
The I 2 C slave device should maintain the last address accessed during the
last I 2 C read or write operation, incremented by one. The first step in the
programming sequence should be to test the i2_cmplt bit for the operationcomplete
status. The next step is to initiate a start sequence by first setting
the i2_start and i2_enbl bits in the I 2 C Control Register and then writing
the device address (bits 7-1) and read bit (bit 0=1) to the I 2 C Transmitter
Data Register. The i2_cmplt bit will be automatically clear with the write
cycle to the I 2 C Transmitter Data Register. The I 2 C Status Register must
now be polled to test the i2_cmplt and i2_ackin bits. The i2_cmplt bit
becomes set when the device address and read bit have been transmitted,
and the i2_ackin bit provides status as to whether or not a slave device
acknowledged the device address. With the successful transmission of the
device address, the I 2 C master controller writes a dummy value
(data=don’t care) to the I 2 C Transmitter Data Register.This causes the I 2 C
master controller to initiate a read transmission from the slave device.
Again, i2_cmplt bit must be tested for proper response. After the I 2 C
master controller has received a byte of data (indicated by i2_datin=1 in
the I 2 C Status Register), the system software may then read the data by
polling the I 2 C Receiver Data Register. The I 2 C master controller does not
acknowledge the read data for a single byte transmission on the I 2 C bus,
but must complete the transmission by sending a stop sequence to the slave
device. This can be accomplished by first setting the i2_stop and i2_enbl
bits in the I 2 C Control Register and then writing a dummy data (data=don’t
care) to the I 2 C Transmitter Data Register. The I 2 C Status Register must
now be polled to test i2_cmplt bit for the operation-complete status. The
stop sequence will relinquish the ASIC master’s possession of the I 2 C bus.
Figure 3-7 shows the suggested software flow diagram for programming
the I 2 C current address read operation.
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