MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
PPC60x Data Parity
PPC60x Address Parity
The Hawk has 8 DP pins for generating and checking PPC60x data bus
parity.
During read cycles that access the SMC, the Hawk generates the correct
value on DP0-DP7 so that each data byte lane along with its corresponding
DP signal has odd parity. This can be changed on a lane basis to even parity
by software bits that can force the generation of wrong (even) parity.
During write cycles to the SMC, the SMC checks each of the eight PPC60x
data byte lanes and its corresponding DP signal for odd parity. If any of the
eight lanes has even parity, the SMC logs the error in the CSR and can
generate a machine check if so enabled.
While normal (default) operation is for the SMC to check data parity only
on writes to it, it can be programmed to check data parity on all reads or
writes to any device on the PPC bus.
Refer to the Data Parity Error Log Register section further on in this
document for additional control register details.
The Hawk has four AP pins for generating and checking PPC60x address
bus parity.
During any address transfer cycle on the PPC60x, the SMC checks each of
the four 8-bit PPC60x address lanes and its corresponding AP signal for
odd parity. If any of the four lanes has even parity, the SMC logs the error
in the CSR and can generate a machine check if so enabled.
Note that the SMC does not generate address parity because it is not a
PPC60x address master.
Refer to the Address Parity Error Log Register section further on in this
document for additional control register details.
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