MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
The Status Register (STATUS) is used to record information for PCI bus
related events. The bits within the STATUS register are defined as follows:
P66M PCI66 MHz. This bit indicates the PHB is capable of
supporting a 66.67 MHz PCI bus.
FAST Fast Back-to-Back Capable. This bit indicates that the
PHB is capable of accepting fast back-to-back
transactions with different targets.
DPAR Data Parity Detected. This bit is set when three
conditions are met: 1) the PHB asserted PERR_ itself or
observed PERR_ asserted; 2) the PHB was the PCI Master
for the transfer in which the error occurred; 3) the PERR
bit in the PCI Command Register is set. This bit is cleared
by writing it to 1; writing a 0 has no effect.
SELTIM DEVSEL Timing. This field indicates that the PHB will
always assert DEVSEL_ as a ‘medium’ responder.
SIGTA Signalled Target Abort. This bit is set by the PCI Slave
whenever it terminates a transaction with a target-abort. It
is cleared by writing it to 1; writing a 0 has no effect.
RCVTA Received Target Abort. This bit is set by the PCI Master
whenever its transaction is terminated by a target-abort. It
is cleared by writing it to 1; writing a 0 has no effect.
RCVMA Received Master Abort. This bit is set by the PCI Master
whenever its transaction (except for Special Cycles) is
terminated by a master-abort. It is cleared by writing it to
1; writing a 0 has no effect.
SIGSE Signaled System Error. This bit is set whenever the PHB
asserts SERR_. It is cleared by writing it to 1; writing a 0
has no effect.
RCVPE Detected Parity Error. This bit is set whenever the PHB
detects a parity error, even if parity error checking is
disabled (see bit PERR in the PCI Command Register). It
is cleared by writing it to 1; writing a 0 has no effect.
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