MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
Some registers have additional requirements for writing. For more
information refer to the register sections in this chapter titled SDRAM
Enable and Size Register (Blocks A,B,C,D), SDRAM Base Address
Register (Blocks A/B/C/D), SDRAM Enable and Size Register (Blocks
E,F,G,H), SDRAM Base Address Register (Blocks E/F/G/H), and SDRAM
Speed Attributes Register.
Since software has no way of controlling refresh/scrub accesses to
SDRAM, the hardware is designed so that updating control bits
coincidentally with refreshes is not a problem.
As with SDRAM control bits, software should not change control bits that
affect ROM/Flash while the affected Block is being accessed. This
generally means that the ROM/Flash size, base address, enable, write
enable, etc. are changed only while executing initially in the reset vector
area ($FFF00000 - $FFFFFFFF).
Initializing SDRAM Related Control Registers
SDRAM Speed Attributes
In order to establish proper SDRAM operation, software must configure
control register bits in Hawk that affect each SDRAM block’s speed, size,
base address, and enable. The SDRAM speed attributes are the same for all
blocks and are controlled by one 32-bit register. The size, base address and
enable can be different for each block and are controlled in individual 8bit
registers.
The SDRAM speed attributes come up from power-up reset initialized to
the slowest settings that Hawk is capable of. This allows SDRAM accesses
to be performed before the SDRAM speed attributes are known.
An example of a need for this is when software requires some working
memory that it can use while gathering and evaluating SDRAM device
data from serial EEPROM’s. Once software knows the SDRAM speed
parameters for all blocks, it should discontinue accessing SDRAM for at
least one refresh period before and after it programs the SDRAM speed
attribute bits.
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