MVME5100 Single Board Computer Programmer's Reference Guide

drr
value
Programming Model
us (64 ms / 8192 rows = 7.8 us). In order for Hawk 1 or 2
to accommodate such SDRAM’s their
CLK_FREQUENCY must be programmed with the CLK
pin (bus clock) frequency divided by two. For example, if
the clock pin frequency is 100 MHz, the
CLK_FREQUENCY register should be programmed
with $32 (100 MHz divided by 2) rather than $64. The
same work-around can, but does not have to be used for
Hawk 3. Hawk 3 includes an additional control bit (drr)
that when set, removes the need for the work-around.
Refer to the following explanation of the drr bit.
drr Double Refresh Rate (Hawk 3 only) When drr is set,
Hawk3’s refresh rate doubles. When drr is cleared,
Hawk3’s refresh rate is normal and matches that of Hawk
1 and 2. Refer to the following examples of DRR and
CLK_FREQUENCY settings with the resulting refresh
rates:
CLK pin
frequency
CLK_FREQUENCY
value
Refresh
Period
7.8us corresponds to 64ms per 8192 rows and 15.6us
corresponds to 64ms per 4096 rows.
Note MVME5100 boards are 100 MHz SBCs.
Comments
0 100 MHz $32 7.8us Hawk1, 2 or 3
0 100 MHz $64 15.6us Hawk1, 2 or 3
1 100 MHz $64 7.8us Hawk3 only
0 66 MHz $21 7.8us Hawk1, 2 or 3
0 66 MHz $42 15.6us Hawk1, 2 or 3
1 66 MHz $42 7.8us Hawk3 only
por por is set by the occurrence of power up reset. It is cleared
by writing a one to it. Writing a 0 to it has no effect.
http://www.motorola.com/computer/literature 3-45
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