MVME5100 Single Board Computer Programmer's Reference Guide

1
Product Data and Memory Maps
Status Register
The MVME5100 implementation of this Register is fully compliant with
the PowerPlus II programming model, with exceptions to bits RD5, RD6
and RD7, as identified in the following table:
An 8-bit status register, accessible through the External Register Set port,
defines the status of the Module.
Table 1-11. MVME5100 Status Register
REG Status Register - FEF88080h
BIT RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7
FIELD
OPER R R R R R R R R
RESET X X X X X X X 0
REQUIRED
OR
OPTIONAL
X X X X X O R R
SYSCON_ System Controller Mode bit. If this bit is set, the module is not the
master of its PCI bus (PCI bus 0). If this bit is cleared, the module
is the master of its PCI bus (PCI bus 0). This bit always reads as
cleared (“0”).
BAUDOUT This is the baud output clock of the TL16C550 UART, referenced
to the 1.8432 MHz UART oscillator. This signal can be used as a
timing reference.
FUSE This bit provides the current state of the FUSE signal. If set, at
least one of the planar fuses or polyswitches is open.
1-24 Computer Group Literature Center Web Site
FUSE
BAUDOUT
SYSCON_