MVME5100 Single Board Computer Programmer's Reference Guide

Data Parity Error Log Register
Address $FEF80068
Bit
Name
DPE_DP
Operation
Reset
Programming Model
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
dpelog
0
0
dpe_tt0
dpe_tt1
dpe_tt2
dpe_tt3
dpe_tt4
R/C
R
R
R
R
R
R
R
0 P
X
0 P
0 P
0 P
0 P
0 P
READ ONLY
0 P
0
0
0
0
0
0
dpe_ckall
dpe_me
R
R
R
R
R
R
R/W
R/W
X
X
X
X
X
X
0 PL
0 PL
GWDP
READ/WRITE
0 PL
dpelog dpelog is set when a parity error occurs on the PPC60x
data bus during a PPC60x data cycle whose parity the
SMC is qualified to check. It is cleared by writing a one to
it or by power-up reset.
dpe_tt0-4 dpe_tt is the value that was on the TT0-TT4 signals when
the dpelog bit was set.
DPE_DP DPE_DP is the value that was on the DP0-DP7 signals
when the dpelog bit was set.
dpe_ckall When dpe_ckall is set, the Hawk checks data parity on all
cycles in which TA_ is asserted. When dpe_ckall is
cleared, the Hawk checks data parity on cycles when TA_
is asserted only during writes to the Hawk.
Note that the Hawk does not check parity during cycles in
which there is a qualified ARTRY_ at the same time as the
TA_.
dpe_me When dpe_me is set, the transition of the dpelog bit from
false to true causes the Hawk to pulse its machine check
interrupt request pin (MCHK0_) true. When dpe_me is
cleared, the Hawk does not assert its MCHK0_ pin based
on the dpelog bit.
GWDP The GWDP0-GWDP7 bits are used to invert the value
that is driven onto DP0-DP7 respectively during reads to
the Hawk. This allows test software to generate wrong
(even) parity on selected byte lanes. For example, to
create a parity error on DH24-DH31 and DP3 during
Hawk reads, software should set GWDP3.
http://www.motorola.com/computer/literature 3-61
3