MVME5100 Single Board Computer Programmer's Reference Guide

Registers
Registers
This section provides a detailed description of all PHB registers. The
section is divided into two parts: the first covers the PPC Registers and the
second covers the PCI Configuration Registers. The PPC Registers are
accessible only from the PPC bus using any single beat valid transfer size.
The PCI Configuration Registers reside in PCI configuration space. These
are primarily accessible from the PPC bus by using the
CONFIG_ADDRESS and CONFIG_DATA registers. The PPC Registers
are described first; the PCI Configuration Registers are described next. A
complete discussion of the MPIC registers can be found later in this
chapter.
It is possible to place the base address of the PPC registers at either
$FEFF0000 or $FEFE0000. Having two choices for where the base
registers reside allows the system designer to use two of the Hawk’s PCI
Host Bridges connected to one PPC60x bus. Please refer to the section
titled PHB Hardware Configuration for more information. All references
to the PPC registers of PHB within this document are made with respect to
the base address $FEFF0000.
The following conventions are used in the Hawk register charts:
❏ R Read Only field.
❏ R/W Read/Write field.
❏ S Writing a ONE to this field sets this field.
❏ C Writing a ONE to this field clears this field.
http://www.motorola.com/computer/literature 2-67
2