MVME5100 Single Board Computer Programmer's Reference Guide

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2 Hawk PCI Host Bridge & Multi-Processor Interrupt Controller The Status Register (STATUS) is used to record information for PCI bus related events. The bits within the STATUS register are defined as follows: P66M PCI66 MHz. This bit indicates the PHB is capable of supporting a 66.67 MHz PCI bus. FAST Fast Back-to-Back Capable. This bit indicates that the PHB is capable of accepting fast back-to-back transactions with different targets. DPAR Data Parity Detected. This bit is set when three conditions are met: 1) the PHB asserted PERR_ itself or observed PERR_ asserted; 2) the PHB was the PCI Master for the transfer in which the error occurred; 3) the PERR bit in the PCI Command Register is set. This bit is cleared by writing it to 1; writing a 0 has no effect. SELTIM DEVSEL Timing. This field indicates that the PHB will always assert DEVSEL_ as a ‘medium’ responder. SIGTA Signalled Target Abort. This bit is set by the PCI Slave whenever it terminates a transaction with a target-abort. It is cleared by writing it to 1; writing a 0 has no effect. RCVTA Received Target Abort. This bit is set by the PCI Master whenever its transaction is terminated by a target-abort. It is cleared by writing it to 1; writing a 0 has no effect. RCVMA Received Master Abort. This bit is set by the PCI Master whenever its transaction (except for Special Cycles) is terminated by a master-abort. It is cleared by writing it to 1; writing a 0 has no effect. SIGSE Signaled System Error. This bit is set whenever the PHB asserts SERR_. It is cleared by writing it to 1; writing a 0 has no effect. RCVPE Detected Parity Error. This bit is set whenever the PHB detects a parity error, even if parity error checking is disabled (see bit PERR in the PCI Command Register). It is cleared by writing it to 1; writing a 0 has no effect. 2-100 <strong>Computer</strong> Group Literature Center Web Site
Revision ID/ Class Code Registers Offset $08 Bit 3 1 3 0 2 9 2 8 2 7 Header Type Register 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 Registers REVID Revision ID. This register identifies the PHB revision level. This register is duplicated in the PPC Registers. CLASS Class Code. This register identifies PHB as the following: Base Class Code $06 PCI Bridge Device Subclass Code $00 PCI Host Bridge Program Class Code $00 Not Used The Header Type Register (Header) identifies the PHB as the following: Header Type: $00 - <strong>Single</strong> Function Configuration Header http://www.motorola.com/computer/literature 2-101 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 0 Name CLASS REVID Operation R R Reset $060000 $01 Offset $0C Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name HEADER Operation R R R R Reset $00 $00 $00 $00 2
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MVME5100 Single Board Computer Prog
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Safety Summary The following genera
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CE Notice (European Community) Moto
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Contents About This Manual Summary
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PCI Slave .........................
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Spurious Vector Register...........
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Address Parity Error Log Register .
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List of Figures Figure 1-1. MVME510
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xviii Table 2-13. Address Modificat
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About This Manual The MVME5100 Sing
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Part Number Description MVME761-011
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8259 Interrupts, and a description
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In this manual, assertion and negat
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1 Product Data and Memory Maps Main
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1 Product Data and Memory Maps Memo
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps PCI
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1 Product Data and Memory Maps L2 C
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1 Product Data and Memory Maps conn
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1 Product Data and Memory Maps to i
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1 Product Data and Memory Maps Requ
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1 Product Data and Memory Maps PROC
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1 Product Data and Memory Maps The
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1 Product Data and Memory Maps Tabl
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1 Product Data and Memory Maps Stat
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1 Product Data and Memory Maps MODR
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1 Product Data and Memory Maps NVRA
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1 Product Data and Memory Maps Geog
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1 Product Data and Memory Maps Boar
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1 Product Data and Memory Maps IPMC
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1 Product Data and Memory Maps Z853
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1 Product Data and Memory Maps IDRE
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2Hawk PCI Host Bridge & Multi- Proc
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Block Diagram PCI Bus MPIC Interfac
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PPC Bus Interface Functional Descri
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PPC Slave Functional Description Ea
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PPC FIFO PPC Transfer Type Transfer
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Functional Description Table 2-2. P
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Table 2-4. PPC Master Read Ahead Op
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PPC Arbiter Pin Name Functional Des
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PPC Parity Functional Description T
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PCI Bus Interface PCI Address Mappi
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Functional Description Each map dec
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Command Types: Functional Descripti
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Fast Back-to-Back Transactions Func
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Functional Description It should be
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Functional Description The PCI Mast
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. Figure 2-6. PCI Spread I/O Addres
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Functional Description The device t
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Functional Description The Hawk’s
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Functional Description Notes 1. “
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. DH07-00 DH15-08 DH23-16 DH31-24 F
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Error Handling Functional Descripti
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Functional Description When not bei
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Functional Description PPC1-Bug>md
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Functional Description From the per
Page 117 and 118: Functional Description ❏ Write po
Page 119 and 120: Multi-Processor Interrupt Controlle
Page 121 and 122: CSR’s Readability Multi-Processor
Page 123 and 124: Interprocessor Interrupts (IPI) 825
Page 127 and 128: Program Visible Registers Multi-Pro
Page 131 and 132: Reset State Multi-Processor Interru
Page 133 and 134: EOI Register Multi-Processor Interr
Page 135 and 136: Registers Registers This section pr
Page 137 and 138: Bit ---> Table 2-16. PPC Register M
Page 139 and 140: General Control-Status/Feature Regi
Page 141 and 142: PPC Arbiter/PCI Arbiter Control Reg
Page 143 and 144: Registers PRKx Parking. This field
Page 145 and 146: Hardware Control-Status/Prescaler A
Page 147 and 148: PPC Error Test/Error Enable Registe
Page 149 and 150: Registers XBTOI PPC Address Bus Tim
Page 151 and 152: Registers PPER PCI Parity Error. Th
Page 153 and 154: PPC Error Attribute Register Regist
Page 155 and 156: PCI Interrupt Acknowledge Register
Page 157 and 158: PPC Slave Offset/Attribute (0, 1 an
Page 159 and 160: The fields within XSADD3 are define
Page 161 and 162: Registers KEY Key. This field is us
Page 163 and 164: PPC6-Bug>mw feff0068 aa88;h Effecti
Page 165 and 166: PCI Registers 3 1 3 0 2 9 2 8 2 7 2
Page 167: PCI Command/ Status Registers Regis
Page 171 and 172: The MPIC Memory Base Address Regist
Page 173 and 174: Registers INV Invalidate Enable. If
Page 175 and 176: Conceptual perspective from the PCI
Page 177 and 178: Registers CONFIG_DATA Register The
Page 179 and 180: 3 1 3 0 2 9 2 8 2 7 2 6 2 5 Table 2
Page 181 and 182: 3 1 3 0 2 9 2 8 2 7 Feature Reporti
Page 183 and 184: Registers M CASCADE MODE. Allows ca
Page 185 and 186: IPI Vector/Priority Registers Offse
Page 187 and 188: Timer Current Count Registers Offse
Page 189 and 190: Timer Vector/Priority Registers Off
Page 191 and 192: Registers MASK MASK. Setting this b
Page 193 and 194: Hawk Internal Error Interrupt Vecto
Page 195 and 196: Current Task Priority Registers Off
Page 197 and 198: 3System Memory Controller (SMC) Int
Page 199 and 200: PowerPC Side D[0:63] DP[0:7] Correc
Page 201 and 202: Figure 3-4. Hawk’s System Memory
Page 203 and 204: Page Holding SDRAM Speeds Functiona
Page 205 and 206: SDRAM Organization Functional Descr
Page 207 and 208: Cache Coherency Functional Descript
Page 209 and 210: Error Logging Functional Descriptio
Page 211 and 212: Functional Description When the wid
Page 213 and 214: Table 3-4. PPC60x to ROM/Flash (64
Page 215 and 216: ROM/Flash Speeds ACCESS TYPE Functi
Page 217 and 218: ACCESS TYPE Functional Description
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I 2 C Byte Write Functional Descrip
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I 2 C Random Read Functional Descri
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I 2 C Current Address Read Function
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I 2 C Page Write Functional Descrip
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I 2 C Sequential Read Functional De
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SDA START DEVICE ADDR M S B BEGIN R
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Chip Configuration Programming Mode
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FEF80070 DPE_A FEF80078 DPE_DH FEF8
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Vendor/Device Register Address $FEF
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SDRAM Enable and Size Register (Blo
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SDRAM Base Address Register (Blocks
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drr value Programming Model us (64
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Normal View of Data (rwcb=0) Check-
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! Caution Programming Model sien Wh
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Programming Model esbt esbt is set
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Scrub Address Register Programming
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Programming Model each half of the
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ROM B Base/Size Register Address Bi
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ROM Speed Attributes Registers Prog
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Data Parity Error Log Register Addr
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Data Parity Error Lower Data Regist
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I 2 C Status Register Programming M
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I 2 C Receiver Data Register Addres
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SDRAM Speed Attributes Register Pro
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Programming Model swr_dpl swr_dpl c
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32-Bit Counter Address $FEF80100 Bi
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Software Considerations When the tb
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SDRAM Size I 2 C EEPROMs Software C
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Software Considerations c. If a CAS
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Software Considerations Notes 1. Us
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Software Considerations 8. Now that
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2. For each of the Blocks A through
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ECC Codes ECC Codes When the Hawk r
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4Hawk Programming Details Introduct
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8259 Interrupts PRI PSIO IRQ Input
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Exceptions Sources of Reset Soft Re
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Endian Issues Hawk Endian Issues Th
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Processor/Memory Domain MPIC’s In
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A Manufacturers’ Documents Manufa
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A Related Specifications Related Sp
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B MVME5100 VPD Reference Informatio
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C Introduction The MVME2700 board,
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Numerics 32-Bit Counter 3-73 SMC 3-
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E ECC Codes Hawk 3-87 SMC 3-11 ECC
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L L2 Cache 1-1, 1-9 L2 Cache SRAM S
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devices, when Big-Endian 2-38 Maste
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om_a_rv and rom_b_rv encoding 3-55
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VME Processor Module MVME510x 1-1 V
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MVME5100 Single Board Computer Programmer's Reference Guide

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