MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
tben Register
Address $FEF88300
Bit
Name
Operation
Reset
The Hawk’s EXTERNAL REGISTER SET interface is
similar to that for ROM/Flash Block A and B. In fact,
another name for the External Register Set is ROM/Flash
Block C. The differences between Blocks A/B and C are
that the following parameters are fixed rather than
programmable for Block C.
1. The device speed for Block C is fixed at 11 Clocks.
2. The width for Block C is fixed at 64 bits.
3. The address range for Block C is fixed at $FEF88000-
$FEF8FFF8 ($FEF98000-$FEF9FFF8 when Hawk is
configured for the alternate CSR base address).
4. Block C is never used for reset vectors.
5. Block C is always enabled unless the tben_en bit is set.
6. Writes to Block C cannot be disabled.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
p1_tben
p0_tben
0
0
0
0
R
R
R/W
R/W
R
R
R
R
X
X
1 PL
1 PL
X
X
X
X
READ ZERO READ ZERO READ ZERO
X X X
The tben Register is only enabled when the tben_en bit in the Revision
ID/General Control Register is set. When tben_en is cleared, the External
Register Set interface is enabled and appears in its designated range.
When tben_en is set, the External Register Set interface is disabled and the
SMC does not respond to accesses in its designated range except that it
responds to the address of this, tben register.
p1_tben When the tben_en bit is set, the L2CLM_ input pin becomes the
P1_TBEN output pin and it tracks the value on p1_tben. When
p1_tben is 0, the P1_TBEN pin is low and when p1_tben is 1,
the P1_TBEN pin is high.
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