MVME5100 Single Board Computer Programmer's Reference Guide

Multi-Processor Interrupt Controller (MPIC)
In the distributed delivery mode, the interrupt is pointed to one or more
processors but it will be delivered to only one processor. Therefore, for
externally sourced or I/O interrupts, multicast delivery is not supported.
The interrupt is delivered to a processor when the priority of the interrupt
is greater than the priority contained in the task register for that processor,
when the priority of the interrupt is greater than any interrupt which is inservice
for that processor, when the priority of that interrupt is the highest
of all interrupts pending for that processor, and when that interrupt is not
in-service for the other processor. If both destination bits are set for each
processor, the interrupt will be delivered to the processor that has a lower
task register priority. Note, due to a deadlock condition that can occur
when the task register priorities for each processor are the same and both
processors are targeted for interrupt delivery, the interrupt will be
delivered to processor 0 or processor 1 as determined by the TIE mode.
Additionally, if priorities are set the same for competing interrupts,
external int. 0 is given the highest priority in hardware followed by
external interrupt 1 through 15 and then followed by timer 0 through timer
3 and followed by IPI 0 and 1. For example, if both ext0 and ext1 interrupts
are pending with the same assigned priority; during the following interrupt
acknowledge cycles, the first vector returned shall be that of ext0 and then
ext1. This is an arbitrary choice.
Block Diagram Description
The description of the MPIC block diagram shown in Figure 2-9 focuses
on the theory of operation for the interrupt delivery logic.
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