MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
PCI Arbiter
Generating PCI Interrupt Acknowledge Cycles
Performing a read from the PIACK register will initiate a single PCI
Interrupt Acknowledge cycle. Any single byte or combination of bytes
may be read from, and the actual byte enable pattern used during the read
will be passed on to the PCI bus. Upon completion of the PCI interrupt
acknowledge cycle, the PHB will present the resulting vector information
obtained from the PCI bus as read data.
The Hawk’s internal PCI arbiter supports up to 8 PCI masters. This
includes Hawk and 7 other external PCI masters. The arbiter can be
configured to be enabled or disabled at reset time by strapping the rd[9] bit
either high for enabled or low for disabled. Table 2-9 describes the pins and
its function for both modes.
Table 2-9. PCI Arbiter Pin Description
Pin Name Pin Reset Internal Arbiter External Arbiter
Type
Direction Function Direction Function
PARBI0 Input - - Input ext req0_ input HAWK gnt_
PARBI1 Input - - Input ext req1_ Input NA
PARBI2 Input - - Input ext req2_ Input NA
PARBI3 Input - - Input ext_req3_ Input NA
PARBI4 Input - - Input ext_req4_ Input NA
PARBI5 Input - - Input ext req5_ Input NA
PARBI6 Input - - Input ext req6_ Input NA
PARBO0 Output Tristate Output ext gnt0_ Output HAWK req_
PARBO1 Output Tristate Output ext gnt1_ Output NA
PARBO2 Output Tristate Output ext gnt2_ Output NA
PARBO3 Output Tristate Output ext gnt3_ Output NA
PARBO4 Output Tristate Output ext gnt4_ Output NA
PARBO5 Output Tristate Output ext gnt5_ Output NA
PARBO6 Output Tristate Output ext gnt6_ Output NA
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