MVME5100 Single Board Computer Programmer's Reference Guide

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About This Manual The MVME5100 Single Board Computer Programmer’s Guide provides the information you will need to program and configure your MVME5100 Single Board Computer. It provides specific programming information and data applicable to this board. This guide provides programming information and other data applicable to the MVME5100. As an added convienience, it also provides details of the chip set (Hawk) programming functions. It is important to note that much of the board’s programming functionality is associated with the Hawk ASIC. Additional programming information can also be found in the following manuals (refer to Appendix A, Related Documentation): ❏ PPCBug Firmware Package User’s Manual ❏ PPCBug Diagnostics Manual ❏ MPC750 RISC Microprocessor User’s Manual ❏ MPC7410 RISC Microprocessor User’s Manual ❏ Universe II User Manual The MVME5100 is a high-performance VME single board computer featuring the Motorola Computer Group (MCG) PowerPlus II architecture with a choice of PowerPC ® processors—either Motorola’s MPC7410 with AltiVec technology for algorithmic intensive computations or the lowpower MPC750 and MPC755. xxi
Page 1 and 2: MVME5100 Single Board Computer Prog
Page 3 and 4: Safety Summary The following genera
Page 5 and 6: CE Notice (European Community) Moto
Page 7 and 8: Contents About This Manual Summary
Page 9 and 10: PCI Slave .........................
Page 11 and 12: Spurious Vector Register...........
Page 13 and 14: Address Parity Error Log Register .
Page 15: List of Figures Figure 1-1. MVME510
Page 18 and 19: xviii Table 2-13. Address Modificat
Page 22 and 23: xxii As of the printing date of thi
Page 24 and 25: Summary of Changes xxiv The followi
Page 26 and 27: Terminology xxvi italic is used for
Page 29 and 30: Introduction 1Product Data and Memo
Page 31 and 32: The following block diagram illustr
Page 33 and 34: Table 1-2. Default Processor Memory
Page 35 and 36: PCI Memory Map VME Memory Map Memor
Page 37 and 38: Processors System Bus The MVME5100
Page 39 and 40: ECC Memory P2 I/O Modes System Bus
Page 41 and 42: Hawk ASIC The Hawk ASIC also provid
Page 43 and 44: PCI Local Bus There are eight poten
Page 45 and 46: PMC/PCI Expansion Slots PCI Local B
Page 47 and 48: PCI Configuration Space Device Numb
Page 49 and 50: Hawk External Register Bus Address
Page 51 and 52: Dual TL16C550 UARTs Required or Opt
Page 53 and 54: MODFAIL Bit Register PCI Local Bus
Page 55 and 56: TBEN Bit Register PCI Local Bus The
Page 57 and 58: Software Readable Header/Switch Reg
Page 59 and 60: Extended Features Register 1 PCI Lo
Page 61 and 62: Extended Features Register 2 PCI Lo
Page 63 and 64: IPMC7xx ISA Bus Resources Z85230 ES
Page 65 and 66: Port Pin IPMC7xx ISA Bus Resources
Page 67: ISA DMA Channels PIB Priority IPMC7
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2 Hawk PCI Host Bridge & Multi-Proc
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3 System Memory Controller (SMC) Bl
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3 System Memory Controller (SMC) HA
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3 System Memory Controller (SMC) Fu
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3 System Memory Controller (SMC) Ta
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3 System Memory Controller (SMC) PP
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3 System Memory Controller (SMC) Er
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3 System Memory Controller (SMC) RO
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System Memory Controller (SMC) Tabl
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3 System Memory Controller (SMC) AC
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3 System Memory Controller (SMC) I
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3 System Memory Controller (SMC) DE
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3 System Memory Controller (SMC) DE
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3 System Memory Controller (SMC) No
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3 System Memory Controller (SMC) ra
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3 System Memory Controller (SMC) CL
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3 System Memory Controller (SMC) EC
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3 System Memory Controller (SMC) 5.
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3 System Memory Controller (SMC) RO
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3 System Memory Controller (SMC) Wr
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3 System Memory Controller (SMC) Op
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3 System Memory Controller (SMC) 51
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3 Syndrome System Memory Controller
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4 Hawk Programming Details MPIC IRQ
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4 Hawk Programming Details PRI PSIO
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4 Hawk Programming Details Error No
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4 Hawk Programming Details Hawk Lit
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ARelated Documentation Motorola Com
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Table A-2. Manufacturers’ Documen
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BMVME5100 VPD Reference Information
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Vital Product Data (VPD) Introducti
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Table B-1. VPD Packet Types (Contin
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Byte Offset Vital Product Data (VPD
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SROM_CRC.C /* * srom_crc - generate
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Serial Presence Detect (SPD) Checks
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Introduction CVMEbus Mapping Exampl
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VMEbus Mapping Example 0000 on the
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I N D E X C cache coherency restric
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I N D E X Global Configuration Regi
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I N D E X functions of Master 2-26
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I N D E X Header Type 2-101 Interpr
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I N D E X SDRAM Enable and Size Reg
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MVME5100 Single Board Computer Programmer's Reference Guide

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