MVME5100 Single Board Computer Programmer's Reference Guide

Fast Back-to-Back Transactions
Functional Description
The PCI Slave supports both of the fundamental target requirements for
fast back-to-back transactions. The PCI Slave meets the first criteria of
being able to successfully track the state of the PCI bus without the
existence of an IDLE state between transactions. The second criteria
associate with signal turn-around timing is met by default since the PCI
Slave functions as a medium responder.
Latency
The PCI Slave does not have any hardware mechanisms in place to
guarantee that the initial and subsequent target latency requirements are
met. Typically this is not a problem since the bandwidth of the PPC bus far
exceeds the bandwidth of the PCI bus.
Exclusive Access
The PCI Slave fully supports the PCI lock function. From the perspective
of the PPC bus, the PHB enables a lock to a single 32 byte cache line.
When a cache line has been locked, the PHB snoops all transactions on the
PPC bus. If a snoop hit happens, the PHB retries the transaction. Note that
the retry is ‘benign’ since there is no follow-on transaction after the retry
is asserted. The PHB contiues to snoop and retry all accesses to the locked
cache line until a valid ‘unlock’ is presented to the PHB and the last locked
cache line transaction is successfully executed.
Note that the PHB locks the cache line that encompasses the actual address
of the locked transaction. For example, a locked access to offset 0x28
creates a lock on the cache line starting at offset 0x20.
From the perspective of the PCI bus, the PCI Slave locks the entire
resource. Any attempt by a non-locking master to access any PCI resource
represented by the PHB results in the PCI Slave issuing a retry.
Parity
The PCI Slave supports address parity error detection, data parity
generation, and data parity error detection.
Cache Support
The PCI Slave does not participate in the PCI caching protocol.
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