MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
ROM A Base/Size Register
Address $FEF80050
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name ROM A BASE
Operation READ/WRITE
Reset $FF0 PL
rom a siz2
rom a siz1
rom a siz0
rom_a_64
R/W
R/W
R/W
R
0 PL
0 PL
0 PL
V P
READ ZERO
rom a we
rom a en
rom_a_rv
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R
Writes to this register must be enveloped by a period of time in which no
accesses to ROM/Flash Block A, occur. A simple way to provide the
envelope is to perform at least two accesses to this or another of the SMC’s
registers before and after the write.
ROM A BASE These control bits define the base address for ROM/Flash
Block A. ROM A BASE bits 0-11 correspond to PPC60x
address bits 0 - 11 respectively. For larger ROM/Flash
sizes, the lower significant bits of ROM A BASE are
ignored. This means that the block’s base address will
always appear at an even multiple of its size. ROM A
BASE is initialized to $FF0 at power-up or local bus reset.
Note that in addition to the programmed address, the first
1Mbyte of Block A also appears at $FFF00000 -
$FFFFFFFF if the rom_a_rv bit is set and the rom_b_rv
bit is cleared.
Also note that the combination of ROM_A_BASE and
rom_a_siz should never be programmed such that
ROM/Flash Block A responds at the same address as the
CSR, SDRAM, External Register Set, or any other slave
on the PowerPC bus.
rom_a_64 rom_a_64 indicates the width of ROM/Flash being used
for Block A. When rom_a_64 is cleared, Block A is 16
bits wide, where each half of SMC interfaces to 8 bits.
When rom_a_64 is set, Block A is 64 bits wide, where
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X
0 PL
0 PL
V P
X
X
X
X
X