MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
PHB Registers
Address modification happens to the originating address regardless of
whether the transaction originates from the PCI bus or the PPC bus. The
three low order address bits are exclusive-ORed with a three-bit value that
depends on the length of the operand, as shown in Table 2-13.
Table 2-13. Address Modification for Little Endian Transfers
Data
Length
(bytes)
Address
Modification
1 XOR with 111
2 XOR with 110
4 XOR with 100
8 no change
Note The only legal data lengths supported in Little-Endian mode
are 1, 2, 4, or 8-byte aligned transfers.
Since this method has some difficulties dealing with unaligned PCIoriginated
transfers, the PPC master of the PHB will break up all unaligned
PCI transfers into multiple aligned transfers into multiple aligned transfers
on the PPC bus.
The PHB registers are not sensitive to changes in Big-Endian and Little-
Endian mode. With respect to the PPC bus (but not always the address
internal to the processor), the PPC registers are always represented in Big-
Endian mode. This means that the processor’s internal view of the PPC
registers appears different depending on which mode the processor
operates.
With respect to the PCI bus, the configuration registers are always
represented in Little-Endian mode.
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