MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
ECC Control Register
Address $FEF80028
Bit
Name
Operation
Reset
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
int
mien
sien
dpien
scien
apien
0
0
0
derc
rwcb
refdis
0
0
0
0
0
R/C
R/W
R/W
R/W
R/W
R/W
R
R
R
R/W
R/W
R/W
R
R
R
R
R
0PL
0PL
0 PL
0 PL
0 PL
0PL
X
X
X
1 PL
0 PL
0 PL
X
X
X
X
X
READ ZERO
mbe_me
0
0
0
0
0
0
0
R/W
R
R
R
R
R
R
R
0 PL
X
X
X
X
X
X
X
refdis When set, refdis causes the refresher and all of its
associated counters and state machines to be cleared and
maintained that way until refdis is removed (cleared). If a
refresh cycle is in process when refdis is updated by a
write to this register, the update does not take effect until
the refresh cycle has completed. This prevents the
generation of illegal cycles to the SDRAM when refdis is
updated.
rwcb rwcb, when set, causes reads and writes to SDRAM from
the PPC60x bus to access check-bit data rather than
normal data. The data path used for reading and writing
check bits is D0-D7. Each 8-bit check-bit location
services 64 bits of normal data. Figure 3-10 shows the
relationship between normal data and check-bit data.
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