MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
Table 3-1. 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100
SDRAMs (CAS_latency of 2) (Continued)
Access Type Access Time Comments
4-Beat Write after 4-Beat Write,
SDRAM Bank Active - Page Hit
1-Beat Read after idle,
SDRAM Bank Inactive
1-Beat Read after idle,
SDRAM Bank Active - Page Miss
1-Beat Read after idle,
SDRAM Bank Active - Page Hit
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Miss
1-Beat Read after 1-Beat Read,
SDRAM Bank Active - Page Hit
1-Beat Write after idle,
SDRAM Bank Active or Inactive
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Miss
1-Beat Write after 1-Beat Write,
SDRAM Bank Active - Page Hit
3-1-1-1 3-1-1-1 for the second burst
write after idle.
2-1-1-1 for subsequent burst
writes.
Notes 1. SDRAM speed attributes are programmed for the
following: CAS_latency = 2, tRCD = 2 CLK Periods, tRP =
2CLK Periods, tRAS = 5 CLK Periods, tRC = 7 CLK
Periods, tDP = 2 CLK Periods, and the swr dpl bit is set in
the SDRAM Speed Attributes Register.
2. The Hawk is configured for “no external registers” on the
SDRAM control signals.
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