MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
The PPC60x bus transfer types generated by the PPC Master depend on the
PCI command code and the INV/GBL bits in the PSATTx registers. The
GBL bit determines whether or not the GBL_ signal is asserted for all
portions of a transaction and is fully independent of the PCI command
code and INV bit. The following table shows the relationship between the
PCI command codes and the INV bit.
Table 2-5. PPC Master Transfer Types
PCI Command Code INV PPC Transfer Type PPC Transfer Size TT0-TT4
Memory Read
Memory Read Multiple
Memory Read Line
Memory Read
Memory Read Multiple
Memory Read Line
Memory Write
Memory Write and
Invalidate
Memory Write
Memory Write and
Invalidate
0 Read Burst/Single Beat 01010
1 Read With Intent to
Modify
Burst/Single Beat 01110
x Write with Kill Burst 00110
x Write with Flush Single Beat 00010
The PPC Master incorporates an optional operating mode called Bus Hog.
When Bus Hog is enabled, the PPC Master continually requests the PPC
bus for the entire duration of each PCI transfer. When Bus Hog is not
enabled, the PPC Master structures its bus request actions according to the
requirements of the FIFO. The Bug Hog mode was primarily designed to
assist with system level debugging and is not intended for normal modes
of operation. It is a brute force method of guaranteeing that all PCI to
PPC60x transactions will be performed without any intervention by host
CPU transactions. Caution should be exercised when using this mode since
the over-generosity of bus ownership to the PPC Master can be detrimental
to the host CPU’s performance. The Bus Hog mode can be controlled by
the XMBH bit within the GCSR. The default state for XMBH is disabled.
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