MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Vendor Identification Register
Offset $01080
Bit 3
1
3
0
2
9
2
8
2
7
2
6
Processor Init Register
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
There are two fields in the Vendor Identification Register which are not
defined for the MPIC implementation but are defined in the MPIC
specification. They are the vendor identification and device ID fields.
STP STEPPING.The stepping or silicon revision number of
Hawk’s MPIC.
P1 PROCESSOR 1. Writing a 1 to P1 will assert the Soft
Reset input of processor 1. Writing a 0 to it will negate the
SRESET signal.
P0 PROCESSOR 0. Writing a 1 to P0 will assert the Soft
Reset input of processor 0. Writing a 0 to it will negate the
SRESET signal.
The Soft Reset input to the 604 is negative edge-sensitive.
2-116 Computer Group Literature Center Web Site
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Name VENDOR IDENTIFICATION
STP
Operation R R R R
Reset $00 $00 $00 $00
Offset $01090
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
Name PROCESSOR INIT
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0 9 8 7 6 5 4 3 2 1 0
Operation R R R R
Reset $00 $00 $00 $00
P0
P1
R/W
R/W
0
0