MVME5100 Single Board Computer Programmer's Reference Guide

Multi-Processor Interrupt Controller (MPIC)
Multi-Processor Interrupt Controller (MPIC)
MPIC Features:
Architecture
The MPIC is a multi-processor structured intelligent interrupt controller.
❏ MPIC programming model
❏ Supports two processors
❏ Supports 16 external interrupts
❏ Supports 15 programmable Interrupt & Processor Task priority
levels
❏ Supports the connection of an external 8259 for ISA/AT
compatibility
❏ Distributed interrupt delivery for external I/O interrupts
❏ Direct/Multicast interrupt delivery for Interprocessor and timer
interrupts
❏ Four Interprocessor Interrupt sources
❏ Four timers
❏ Processor initialization control
The PCI Slave of the PHB implements two address decoders for placing
the MPIC registers in PCI IO or PCI Memory space. Access to these
registers requires PPC and PCI bus mastership. These accesses include
interrupt and timer initialization and interrupt vector reads.
The MPIC receives interrupt inputs from 16 external sources, four
interprocessor sources, four timer sources, and one Hawk internal error
interrupt source. The externally sourced interrupts 1 through 15 have two
modes of activation; low level or active high positive edge. External
interrupt 0 can be either level or edge activated with either polarity. The
Hawk internal error interrupt request is an active low level sensitive
interrupt. The Interprocessor and timers interrupts are event activated.
http://www.motorola.com/computer/literature 2-51
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