MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Architectural Notes
The hardware and software overhead required to update the task priority
register synchronously with instruction execution may far outweigh the
anticipated benefits of the task priority register. To minimize this
overhead, the interrupt controller architecture should allow the task
priority register to be updated asynchronously with respect to instruction
execution. Lower priority interrupts may continue to occur for an
indeterminate number of cycles after the processor has updated the task
priority register. If this is not acceptable, the interrupt controller
architecture should recommend that, if the task priority register is not
implemented with the processor, the task priority register should only be
updated when the processor enters or exits an idle state.
Only when the task priority register is integrated within the processor, such
that it can be accessed as quickly as the MSRee bit, for example, should
the architecture require the task priority register be updated synchronously
with instruction execution.
Effects of Interrupt Serialization
All external interrupt sources that are level sensitive must be negated at
least N PCI clocks prior to doing an EOI cycle for that interrupt source,
where N is equal to the number of PCI clocks necessary to scan in the
external interrupts. In the example shown, 16 external interrupts are
scanned in, N = 16. Serializing the external interrupts causes a delay
between the time that the external interrupt source changes level and when
MPIC logic actually sees the change. Spurious interrupts can result if an
EOI cycle occurs before the interrupt source is seen to be negated by MPIC
logic.
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