MVME5100 Single Board Computer Programmer's Reference Guide

Functional Description
❏ Write posted transactions originating from the processor bus are
flushed by the nature of the FIFO architecture. The PHB will hold
the processor with wait states until the PCI bound FIFO is empty.
❏ Write posted transactions originated from the PCI bus are flushed
whenever the PCI slave has accepted a write-posted transaction and
the transaction has not completed on the PPC bus.
The PPC Slave address decode logic settles out several clocks after the
assertion of TS_, at which time the PPC Slave can determine the
transaction type. If it is a read and XFBR is enabled, the PPC Slave will
look at the ps_fbrabt signal. If this signal is active, the PPC Slave will retry
the processor.
When the PFBR bit is set, PHB will handle read transactions originating
from the PCI bus in the following manner:
❏ Write posted transactions originating from the PCI bus are flushed
by the nature of the FIFO architecture. The PHB will hold the PCI
Master with wait states until the PPC bound FIFO is empty.
❏ Write posted transactions originated from the PPC60x bus are
flushed in the following manner. The PPC Slave will set a signal
called xs_fbrabt anytime it has committed to performing a posted
write transaction. This signal will remain asserted until the PCI
bound FIFO count has reached zero.
The PCI Slave decode logic settles out several clocks after the assertion of
FRAME_, at which time the PCI Slave can determine the transaction type.
If it is a read and PFBR is enabled, the PCI Slave will look at the xs_fbrabt
signal. If this signal is active, the PCI Slave will retry the PCI Master.
PHB Hardware Configuration
Hawk has the ability to perform custom hardware configuration to
accommodate different system requirements. The PHB has several
functions that may be optionally enabled or disabled using passive
hardware external to Hawk. The selection process occurs at the first rising
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