MVME5100 Single Board Computer Programmer's Reference Guide

SDRAM Base Address Register (Blocks A/B/C/D)
Programming Model
Address
Bit
$FEF80018
Name RAM A BASE RAM B BASE RAM C BASE RAM D BASE
Operation READ/WRITE READ/WRITE READ/WRITE READ/WRITE
Reset 0 PL 0 PL 0 PL 0 PL
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Writes to this register must be enveloped by a period of time in which no
accesses to SDRAM occur. The requirements of the envelope are that all
SDRAM accesses must have completed before the write starts and none
should begin until after the write is done. A simple way to do this is to
perform at least two read accesses to this, or another register, before and
after the write.
Additionally, sometime during the envelope, before or after the write, all
of the SDRAMs’ open pages must be closed and the Hawk’s open page
tracker reset. The way to do this is to allow enough time for at least one
SDRAM refresh to occur by waiting for the 32-Bit Counter, described
further on in this chapter, to increment at least 100 times. The wait period
must happen during the envelope.
RAM A/B/C/D BASE These control bits define the base address for their block’s
SDRAM. RAM A/B/C/D BASE bits 0-7/8-15/16-23/24-
31 correspond to PPC60x address bits 0 - 7. For larger
SDRAM sizes, the lower significant bits of A/B/C/D
BASE are ignored. This means that the block’s base
address will always appear at an even multiple of its size.
Remember that bit 0 is MSB.
Note that RAM_E/F/G/H_BASE are located at
$FEF800C8 (refer to the section on SDRAM Base
Address Register (Blocks E/F/G/H). They operate the
same for blocks E-H as these bits do for blocks A-D.
Also note that the combination of RAM_X_BASE and
ram_x_siz should never be programmed such that
SDRAM responds at the same address as the CSR,
ROM/Flash, External Register Set, or any other slave on
the PowerPC bus.
http://www.motorola.com/computer/literature 3-43
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