MVME5100 Single Board Computer Programmer's Reference Guide

I 2 C Status Register
Programming Model
i2_stop When set, the I 2 C master controller generates a stop sequence
on the I 2 C bus on the next dummy write (data=don’t care) to
the I 2 C Transmitter Data Register and clears the i2_cmplt bit
in the I 2 C Status Register. After the stop sequence has been
transmitted, the I 2 C master controller will automatically clear
the i2_stop bit and then set the i2_cmplt bit in the I 2 C Status
Register.
i2_ackout When set, the I 2 C master controller generates an acknowledge
on the I 2 C bus during read cycles. This bit should be used only
in the I 2 C sequential read operation and must remain cleared
for all other I 2 C operations. For I 2 C sequential read operation,
this bit should be set for every single byte received except on
the last byte in which case it should be cleared.
i2_enbl When set, the I 2 C master interface will be enabled for I 2 C
operations. If clear, reads and writes to all I 2 C registers are
still allowed but no I 2 C bus operations will be performed.
Address $FEF800A0
Bit 0
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
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31
Operation READ ZERO READ ZERO READ ZERO R RRRRRRR
Reset X X X
0
0
0
0
i2_datin
i2_err
i2_ackin
i2_cmplt
X
X
X
X
0 PL
0 PL
0 PL
1 PL
i2_datin This bit is set whenever the I 2 C master controller has
successfully received a byte of read data from an I 2 C bus slave
device. This bit is cleared after the I 2 C Receiver Data Register
is read.
i2_err This bit is set when both i2_start and i2_stop bits in the I 2 C
Control Register are set at the same time. The I 2 C master
controller will then clear the contents of the I 2 C Control
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