MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
cl3 When cl3 is cleared, the SMC assumes that the SDRAM runs
with a CAS_ latency of 2. When cl3 is set, the SMC assumes that
it runs with a CAS_ latency of 3. Note that writing so as to
change cl3 from 1 to 0 or vice-versa causes the SMC to perform
a mode-register-set operation to the SDRAM array. The moderegister-set
operation updates the SDRAM’s CAS latency to
match cl3.
trc0,1,2 Together trc0,1,2 determine the minimum number of clock
cycles that the SMC assumes the SDRAM requires to satisfy its
Trc parameter. These bits are encoded as follows:
Table 3-16. Trc Encoding
trc0,1,2 Minimum Clocks for Trc
%000 8
%001 9
%010 10
%011 11
%100 reserved
%101 reserved
%110 6
%111 7
tras0,1 Together tras0,1 determine the minimum number of clock
cycles that the SMC assumes the SDRAM requires to satisfy its
tRAS parameter. These bits are encoded as follows:
Table 3-17. tras Encoding
tras0,1 Minimum Clocks for tras
%00 4
%01 5
%10 6
%11 7
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