MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Programming Notes
External Interrupt Service
The following summarizes how an external interrupt is serviced:
❏ An external interrupt occurs.
❏ The processor state is saved in the machine status save/restore
registers. A new value is loaded into the Machine State Register
(MSR). The External Interrupt Enable bit in the new MSR (MSRee)
is set to zero. Control is transferred to the O/S external interrupt
handler.
❏ The external interrupt handler calculates the address of the Interrupt
Acknowledge register for this processor (MPIC Base Address +
0x200A0) + (processor ID shifted left 12 bits).
❏ The external interrupt handler issues an Interrupt Acknowledge
request to read the interrupt vector from the Hawk’s MPIC. If the
interrupt vector indicates the interrupt source is the 8259, the
interrupt handler issues a second Interrupt Acknowledge request to
read the interrupt vector from the 8259. The Hawk’s MPIC does not
interact with the vector fetch from the 8259.
❏ The interrupt handler saves the processor state and other interruptspecific
information in system memory and re-enables for external
interrupts (the MSRee bit is set to 1). MPIC blocks interrupts from
sources with equal or lower priority until an End-of-Interrupt is
received for that interrupt source. Interrupts from higher priority
interrupt sources continue to be enabled. If the interrupt source is the
8259, the interrupt handler issues an EOI request to the MPIC. This
resets the In-Service bit for the 8259 within the MPIC and allows it
to recognize higher priority interrupt requests, if any, from the 8259.
If none of the nested interrupt modes of the 8259 are enabled, the
interrupt handler issues an EOI request to the 8259.
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