MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
PRI Priority. If set, the PPC Arbiter will impose a rotating
between CPU0 grants. If cleared, a fixed priority will be
established between CPU0 and CPU1 grants, with CPU0
having a higher priority than CPU1.
PRKx Parking. This field determines how the PPC Arbiter will
implement CPU parking. The encoding of this field is
shown in the table below.
PRK CPU Parking
00 None
01 Park on last CPU
10 Park always on CPU0
11 Park always on CPU1
ENA Enable. This read only bit indicates the enabled state of
the PPC Arbiter. If set, the PPC Arbiter is enabled and is
acting as the system arbiter. If cleared, the PPC Arbiter is
disabled and external logic is implementing the system
arbiter. Refer to the section titled PHB Hardware
Configuration for more information on how this bit gets
set.
The PCI Arbiter Register (PARB) provides control and status for the PCI
Arbiter. Refer to the section titled PCI Arbiter for more informatiion. The
bits within the PARB register are defined as follows:
PRIx Priority. This field is used by the PCI Arbiter to establish
a particular bus priority scheme. The encoding of this field
is shown in the following table.
PRI Priority Scheme
00 Fixed
01 Round Robin
10 Mixed
11 Reserved
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