MVME5100 Single Board Computer Programmer's Reference Guide

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Table 2-13. Address Modification for Little Endian Transfers ............................... 2-40
Table 2-14. WDTxCNTL Programming ................................................................. 2-44
Table 2-15. PHB Hardware Configuration .............................................................. 2-50
Table 2-16. PPC Register Map for PHB.................................................................. 2-68
Table 2-17. PCI Configuration Register .................................................................. 2-97
Table 2-18. PCI I/O Register ................................................................................... 2-98
Table 2-19. MPIC Register Map............................................................................ 2-110
Table 2-20. Cascade Mode Encoding .................................................................... 2-115
Table 2-21. Tie Mode Encoding ............................................................................ 2-115
Table 3-1. 60x Bus to SDRAM Estimated Access Timing at 100 MHz with PC100
SDRAMs (CAS_latency of 2) ................................................................................... 3-7
Table 3-2. Error Reporting....................................................................................... 3-12
Table 3-3. PPC60x to ROM/Flash (16 Bit Width)
Address Mapping..................................................................................................... 3-16
Table 3-4. PPC60x to ROM/Flash (64 Bit Width)
Address Mapping..................................................................................................... 3-17
Table 3-5. PPC60x Bus to ROM/Flash Access Timing
(120ns @ 100 MHz) ................................................................................................ 3-19
Table 3-6. PPC60x Bus to ROM/Flash Access Timing
(80ns @ 100 MHz) .................................................................................................. 3-20
Table 3-7. PPC60x Bus to ROM/Flash Access Timing
(50ns @ 100 MHz) .................................................................................................. 3-20
Table 3-8. PPC60x Bus to ROM/Flash Access Timing
(30ns @ 100 MHz) .................................................................................................. 3-21
Table 3-9. Register Summary .................................................................................. 3-36
Table 3-10. Block_A/B/C/D/E/F/G/H Configurations ............................................ 3-42
Table 3-11. ROM Block A Size Encoding .............................................................. 3-55
Table 3-12. rom_a_rv and rom_b_rv encoding ....................................................... 3-55
Table 3-13. Read/Write to ROM/Flash.................................................................... 3-56
Table 3-14. ROM Block B Size Encoding .............................................................. 3-58
Table 3-15. ROM Speed Bit Encodings .................................................................. 3-60
Table 3-16. Trc Encoding ........................................................................................ 3-70
Table 3-17. tras Encoding........................................................................................ 3-70
Table 3-18. Deriving tras, trp, trcd and trc Control Bit Values from SPD
Information .............................................................................................................. 3-79
Table 3-19. Programming SDRAM SIZ Bits .......................................................... 3-82
Table 3-20. Address Lists for Different Block Size Checks.................................... 3-86
Table 3-21. Syndrome Codes Ordered by Bit in Error ............................................ 3-87
Table 3-22. Single Bit Errors Ordered by Syndrome Code..................................... 3-88