MVME5100 Single Board Computer Programmer's Reference Guide

3
System Memory Controller (SMC)
SDA
START
DEVICE ADDR
M
S
B
BEGIN
READ I 2 C STATUS REG
CMPLT=1? N
LOAD “$09” (START CONDITION) TO
I 2 C CONTROL REG
LOAD “DEVICE ADDR+WR BIT” TO
I 2 C TRANSMITTER DATA REG
LOAD “WORD ADDR x” TO
I 2 C TRANSMITTER DATA REG
Y
READ I 2 C STATUS REG
CMPLT=ACKIN=1?
Y
READ I 2 C STATUS REG
CMPLT=ACKIN=1?
Y
A
W
C
R
K
LOAD “$09” (REPEATED START
CONDITION) TO I 2 C CONTROL REG
LOAD “DEVICE ADDR+RD BIT” TO
I 2 C TRANSMITTER DATA REG
WORD ADDR x
N
N
*
*
DEVICE ADDR
A M
C START S
K B
READ I 2 C STATUS REG
CMPLT=ACKIN=1?
LOAD “$05” (STOP CONDITION) TO
I 2 C CONTROL REG
LOAD “DUMMY DATA” TO
I 2 C TRANSMITTER DATA REG
READ I 2 C STATUS REG
CMPLT=1?
Figure 3-6. Programming Sequence for I 2 C Random Read
3-26 Computer Group Literature Center Web Site
A
C
K
END
Y
Y
N
LOAD “DUMMY DATA” TO
I 2 C TRANSMITTER DATA REG
READ I 2 C STATUS REG
CMPLT=DATIN=1?
READ I 2 C RECEIVER DATA REG
Y
R
D
DATA x
N
N
N
O
A
C
K
STOP
ACK and DATA from Slave Device
(*): Stop condition should be generated to abort the transfer after a software wait loop (~1ms) has been expired
*
*