MVME5100 Single Board Computer Programmer's Reference Guide

2
Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
MPIC I/O Base Address Register
Offset $10
Bit 3
1
3
0
2
9
2
8
2
7
The MPIC I/O Base Address Register (MIBAR) controls the mapping of
the MPIC control registers in PCI I/O space.
IO/MEM IO Space Indicator. This bit is hard-wired to a logic one
to indicate PCI I/O space.
RES Reserved. This bit is hard-wired to zero.
BASE Base Address. These bits define the I/O space base
address of the MPIC control registers. The MIBAR
decoder is disabled when the BASE value is zero.
MPIC Memory Base Address Register
2
6
2
5
Name MIBAR
BASE
2
4
2
3
Operation R/W R
2
2
Reset $0000 $0000
Offset $14
Bit 3
1
3
0
2
9
2
8
2
7
2
6
2
5
Name MMBAR
BASE
2
4
2
3
Operation R/W R
Reset $0000 $0000
2
2
2
1
2
1
2
0
2
0
1
9
1
9
1
8
1
8
2-102 Computer Group Literature Center Web Site
1
7
1
7
1
6
1
6
1
5
1
5
1
4
1
4
1
3
1
3
1
2
1
2
1
1
1
1
1
0 9 8 7 6 5 4 3 2 1 0
IO/MEM
RES
R
R
1
0
1
0 9 8 7 6 5 4 3 2 1 0
IO/MEM
MTYP0
MTYP1
PRE
R
R
R
R
0
0
0
0